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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 35/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
35
USB Wrapper Registers
The following registers are found in the USB wrapper block
and control the overall performance of the USB HW block.
They provide status information, allow interrupt masking
and DMA programming for fast data transfers between the
DPRAM and the endpoint buffers.
Table
SLP_MD_EN: Sleep mode control
addr 5000000h
R/W
8-bits
Note:
Default: 00h
Table
GLB_IRQ_MSK: Global Interrupt Master register
addr 5000004h
R/W
16-bits
Note:
Default: 00h
These registers allow interrupt masking for the following
interrupts sources:
1.
INTERRUPT line from USB protocol handler.
2.
USB reset (USB_RES). A USB reset signal is
asserted from USB protocol handler when the USB
host requests it by forcing both the differential USB
network signals to low level.
3.
Suspend: A USB device enters in suspend only
when requested by the USB host through bus inac-
tivity for at least 3ms.
4.
Resume: a J to K state change on the USB port sig-
nals resume.
Table
IRQ_STAT: Master Interrupt Status
addr 5000008h
R
16-bits
Note:
Default: 00h
Table
RES_STAT: Reset Status
addr 500000Ch
R/W
8-bits
Note:
Default: 00h
Table
DEF_EP_PAIRS: Endpoint pairs definition
addr 5000010h
R/W
8-bits
Bits 7...6
Bit 5
Reserved
Put the usb module in sleep
mode
Reserved
SLP
Bits 4...0
Bits
15...11
Bit 10
Reserved
TDMA_IEN
Transmit DMA Interrupt
Enable
Receive DMA Interrupt Enable
When this bit is high, the USB
reset interrupts are enabled
Reserved
When this bit is high, it allows
the INTERRUPT line from the
USB protocol handler to cause
interrupts
Reserved
If this bit is high, an interrupt is
generated when the the USB
enters suspend mode
If this bit is high, an interrupt is
generated when the USB
enters resume mode
Bit 9
Bit 8
RDMA_IEN
URES_INT
Bit 7
Bit 6
INT_EN
Bits 5...2
Bit 1
SUSP_INT
Bit 0
RSM_INT
Bits
15...11
Bit 10
Bit 9
Bit 8
Reserved
TDMA_TC
RDMA_TC
SUS_RES_ST
Transmit DMA complete
Receive DMA complete
Indicates the current status of
the USB block
When this bit is high, the USB
is in Suspend mode while,
when low, the USB has
resumed
Reserved
The INTERRUPT line from the
USB protocol handler is
asserted
Reserved
When this bit is high, the USB
has entered the suspend state
When this bit is high, the USB
has entered the resume state
Bit 7
Bit 6
INTER_LINE
Bits 5...2
Bit 1
SUSP
Bit 0
RSM
Bits 7...5
Bit 4
Reserved
Set, when USB module
enters reset state
Reserved
USB_RES
Bits 3...0
Bits 7...4
Bit 3
Reserved
When this bit is high, the EP3
supports an OUT and an IN
endpoint. In this case the EP6
is used as the IN endpoint
When this bit is high, the EP2
supports an OUT and an IN
endpoint. In this case the EP5
is used as the IN endpoint
EP3_EN_PAIR
Bit 2
EP2_EN_PAIR
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