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参数资料
型号： AT76C551
厂商： ATMEL CORP
元件分类： 通信及网络
英文描述： Single Chip Bluetooth Controller(单芯片蓝牙技术控制器)
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP176
封装： LQFP-176
文件页数： 43/51页
文件大小： 845K
代理商： AT76C551
AT76C551
43
Protocol Mode Register (US_PMR)
Table
Protocol Mode REgister (US_PMR)
Addr: 70000C hex
R/W
8-bits
Note:
Default Value: 00 hex
Table
Mode Register (US_MR)
Addr: 700010 hex
R/W
8-bits
Note:
Default Value: 00 hex
Table
Control Status Register (US_CSR)
Addr: 700014 hex
R/W
8-bits
Note:
Default Value: 00 hex
Table
Control Register (US_CR)
Addr: 700018 hex
R/W
8-bits
Bits
7
…
6
CHL[1:0]
Character length
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
Number of stop bits
00: 1 bit time
01: 1,5 bit time
10: 2 bit time
11: Reserved
Parity mode
00: Normal parity
01: Parity forced
10: No parity
11: Multi drop
Parity type. In normal parity
mode this bit is used for the
determination of parity. In force
parity mode this bit is forced to
be the parity bit
Reserved
Bits
5
…
4
SBN[1:0]
Bits
3
…
2
PM[1:0]
Bit 1
Res
Bit 0
LSB
Bits
7
…
6
CHM[1:0]
Channel mode
00: Normal
01: Automatic echo
10: Local loop-back
11: Remote loop-back
Reserved
Bits
5
…
0
Bit 7
TXE
Transmitter empty. When set
indicates that both the Transmit
Holding Register US_THR and
Transmit Shift Register are
empty
Bit 6
RXTO
Receive Time-out. When set
indicates that a receive time-out
condition has occurred
Parity Error. When set indicates
that a parity error has occurred
Framing Error. When set
indicates that a framing error
has occurred (start or stop bits
has been received with errors)
Overrun Error. When set
indicates that an overrun error
has occurred. This means that
the Receive Holding Register is
being written with a new value,
while the previous one has not
been read
Receive Break. When set
indicates that a break condition
has occurred during reception
Transmit holding register ready.
When set indicates that the
contents of the Transmit Holding
Register have been transferred
to the Transmit Shift Register
Receive holding register ready.
When set indicates that the
Receive Holding Register is full.
In order to clear this bit you must
empty the RHR (or the FIFO if it
is enabled) by reading the
US_RHR
register.
Bit 5
PE
Bit 4
FE
Bit 3
OE
Bit 2
RBR
Bit 1
THR
Bit 0
RHR
Bit 7
RXEN
Enable. When set enables the
receiver block of UART
Reset Line Error Status bits.
When set resets the PE, FE, OE
bits of US_CSR register
Tx enable. When set enables
the transmitter block of UART
Restart Time-out. When set
resets the time-out counter for a
new time-out period
Tx Reset. When set resets the
transmit logic
Rx Reset. When set resets the
receive logic
Stop Break. Break command to
the transmit logic. When set,
stops break condition
Bit 6
RLES
Bit 5
TXEN
Bit 4
RSTO
Bit 3
TXRS
Bit 2
RXRS
Bit 1
SPB
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PDF描述
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