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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 37/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
37
Table
USB_TDMA_LENR: Transmit DMA packet length
transferred
addr 5000048h
R
8-bits
Note:
Default: 00h
After the end of a DMA, the contents of this register reflect
the number of bytes that have been transferred from main
system memory to the transmit FIFO.
Table
USB_TDMA_EN: Transmit DMA Enable
addr 500004Ch
R/W
8-bits
Note:
Default: 00h
This bit is reset after the completion of the DMA.
Table
FRM_NUM_H : Frame Number High Register
addr 50003F4h
W
8-bits
Note:
Default: 00h
Table
FRM_NUM_L : Frame Number Low Register
addr 50003F0h
W
8-bits
Note:
Default: 00h
Table
GLB_STATE: Global State Register
addr 50003ECh
8-bits
Note:
Default: 00h
Table
SPRSR : Suspend/Resume Register
addr 50003E8h
W
8-bits
Note:
Default: x0h
Table
SPRSIE : Suspend/Resume Interrupt Enable Regis-
ter
addr 50003E4h
R
8-bits
Bits 7...0
UTDL[7:0]
Transmit DMA transferred
length
Bits 7...2
Bit 1
Bit 0
Reserved
Reserved
Activates transmit DMA (DMA
for an IN endpoint)
TDMAEN
Bits
7...3
Reserved
Bits 2...0
FCH[10:8]
This is the upper 3 bits of the
11 bit frame number of SOF
packet
Bits 7...3
Bits
2...0
Reserved
This is the lower 8-bits of
the 11 bit frame number of
SOF packet
FCL[7:0]
Bits 7...4
Bit 3
W
Reserved
Set by the H/W when a
Resume is send in the USB
bus during Remote Wake-up
feature (13 ms).
Remote Wake-up Enable.
This bit is set if the Host
enables the function
’
s remote
wake-up feature.
Configured. This bit is set by
the firmware after a valid
SET_CONFIGURATION
request is received. It is
cleared by a reset or by a
SET_CONFIGURATION with
a value of 0.
Function Address Enable.
This bit is set by firmware after
the status phase of a
SET_ADRESS request
transaction. The Host will use
the new address starting at
the next transaction.
RSMINPR
Bit 2
R
RMWUPE
Bit 1
R
CONFG
Bit 0
R
FADD Enable
Bits 7...4
Bit 3
Bit 2
Reserved
Start Of Frame Interrupt
Received External Resume.
The USB H/W sets this bit to
denote an External Resume
Interrupt. If RMWUPE =1, a
RESUME signal is send in
USB BUS.
Received Resume. The USB
H/W sets this bit when a USB
resume signaling is detected
at its port.
Suspend. The USB H/W sets
this bit when it detects no SOF
for 3ms. The USB macro
enters in SUSPEND MODE,
the processor has to go in
SLEEP mode.
SOF INT
EXT RSM
Bit 1
RCVD RSM
Bit 0
SUSP
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