参数资料
型号: AT76C551
厂商: ATMEL CORP
元件分类: 通信及网络
英文描述: Single Chip Bluetooth Controller(单芯片蓝牙技术控制器)
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP176
封装: LQFP-176
文件页数: 9/51页
文件大小: 845K
代理商: AT76C551
AT76C551
9
NREG
I
Attribute Memory Select - Driven by the host to select between Attribute mem-
ory or I/O space (REG asserted) and Common memory (REG deasserted) in
the device and the PCMCIA card.
Extend Bus Cycle - This signal is asserted by the device to delay completion of
the access cycle currently in progress.
Input Acknowledge - It is asserted when the BT device is selected and can
respond to an I/O read cycle at the address currently apllied on the address
bus. It is used by the host to control the enabe of any input buffer between the
card and the CPU. It will be inactive during card configuration.
Interrupt Request - Asserted by the chip to indicate to the host that software
service should take place.
NWAIT
O
NINPACK
O
NIREQ
O
UART Interface Pins
U_CTS_
I
Clear To Send
U_DSR_
I
Data Set Ready
U_DTR_
O
Data Terminal Ready
U_RI_
I
Ring Indicator
U_RTS_
O
Request To Send
USART_RX
I
serial input port
USART_TX
O
serial output port
U_CD_
I
Carrier Detect
USB Interface Pins
DP
B
Upstream Plus USB I/O. This pin should be connected to CEXT through an external
1.5K pull up resistor. DPLUS and DMINUS form the differential signal pin pairs
connected to the Host Controller or an upstream Hub.
DM
B
Upstream Minus USB I/O.
Analog Voice CODEC Pins
VC_IN
LOG I
Voice input
VC_OUT
LOG O
Voice output
Digital Voice CODEC Pins
ADO
O
Data Transmit
ADI
I
Data Receive
ACLK
O
Master Clock - Out
ABCLK
O
Bit clock - Out
ASYNC
O
Frame Sync - Out
ACLK_IN
I
Master Clock -In
ABCLK_IN
I
Bit Clock - In
ASYNC_IN
I
Frame Sync - In
JTAG Pins
DB_DATA
O
Debug data port.
NAME
TYPE
DESCRIPTION
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