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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 23/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
23
Table
CtrlStatus2
Addr: 60001C hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Table
CLKN
Addr: 600020 hex
R
32-bits
Note:
Default Value: 00000000 hex
Table
CLOCK
Addr: 600024 hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Table
CLKPhase
Addr: 600028 hex
R/W
32-bits
Note:
Default Value: 00000000 hex
Bits
31...20
Bit 19
R
Reserved
AccCodeBusy
Set by HW during access
code calculation or
transmission
Set by HW during
ciphering/deciphering.
Bit 18
R
Bit 17
R
Bit 16
R
Bit 15
R
Bits
14...13
W
CipherBusy
E_funBusy
Set by HW during
E_function calculation
TxDataBusy
Set by HW while TX data is
being streamed out.
RxDataBusy
Set by HW while RX data is
being streamed in.
E_funType
Selects the type of E
function to be calculated.
00: E1 (used for
authentication)
01: E21 (used for link key
generation)
10: E22 (used for link key
generation)
11: E3 (used for encryption
key generation)
Set by firmware to start E
function calculation.
Reset by HW when
calculation is complete.
0: No encryption used
1: Packet payload is
encrypted in TX and
decrypted in RX
Sliding correlator threshold
value, default = 51
Sets sliding correlator
sensitivity.
Set by firmware to start
access code recovery from
LAP and FHS packet parity
bits.
Auto-clear.
Set by firmware to start
access code calculation
from BD_ADDR only.
Auto-clear.
Bit 12
R/W
EfunEnblBusy
Bit 11
W
CipherMode
Bits
10...4
W
CorrelThresh
Bit 3
W
GetFHS_
syncword
Bit 2
W
EvalAccCode
Bit 1
W
AccCodeType
0: Access code TXed (and
loaded on sliding correlator)
has no trailer bits, thus
access code size is 68 bits.
1: Access code TXed (and
loaded on sliding correlator)
has trailer bits, thus access
code size is 72 bits.
0: The packet expected to
be RXed is not an FHS
packet.
1: An FHS packet RX is
expected.
Bit 0
W
RxFHS
Bits
31...28
Bits
27
…
0
Reserved
CLKN[27:0]
Provides native clock
current value to firmware
Bits
31...28
Bits
27
…
0
Reserved
CLOCK[27:0]
In this register specific
fields of device
’
s native
clock or of transmitter
’
s
estimated in receiver
native clock are set.
Bits
31...15
Bits
14
…
0
Reserved
CLKPhase[14:0]
Provides native clock
phase current value to
firmware. Native clock
phase is estimated in
system clock cycles
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