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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 36/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
36
Note:
Default: 00h
This 3-bit register defines which endpoints support both IN
and OUT connections. Only the endpoints 1-3 support end-
point pair addressing. There is a correspondence between
endpoints 1 to 3 and endpoints 4 to 6, such that when e.g.
endpoint 1 pair addressing is enabled, endpoint 4 becomes
the pair endpoint. In this case, the endpoint 1 should be
configured as an OUT endpoint, while endpoint 4 is an IN
endpoint.
This correspondence is transparent to the USB host which
considers that there are two endpoints at address 0x01, an
OUT
Table
USB_RDMA_LEN: Receive DMA packet length
requested
addr 500001Ch
R/W
16-bits
Note:
Default: 00h
ARM programs this register with the number of bytes to be
transferred during the next DMA.
Table
USB_DMA_FADD: DMA target Endpoint address
addr 5000020h
R/W
16-bits
Note:
Default: 00h
This register is programmed with the address of the End-
point FIFO Register of the USB block that the DMA opera-
tion is going to transfer bytes from/to. The addresses of the
six endpoints supported by the USB block are listed below:
Table
USB_RDMA_LENR: Receive DMA packet length
transferred
addr 5000024h
R
8-bits
Note:
Default: 00h
The contents of this register after the end of a DMA reflect
the number of bytes that have been transferred.
Table
USB_RDMA_EN
addr 5000028h
R/W
8-bits
Note:
Default: 00h
Table
USB_DMA_RADD: RAM Targer Address for DMA
cycles
addr 5000040h
R/W
32-bits
Note:
Default: 00h
Table
USB_TDMA_LEN: Transmit DMA packet length
requested
addr 5000044h
R/W
16-bits
Note:
Default: 00h
The ARM programs this register with the number of bytes
to be transferred during the next DMA.
Bit 1
EP1_EN_PAIR
When this bit is high, the EP1
supports an OUT and an IN
endpoint. In this case the EP4
is used as the IN endpoint
Bit 0
Reserved
Bits
15...9
Bits 8...0
Reserved
URDL[8:0]
USB Receive DMA Length
Bits 7...0
FAD[7:0]
USB Target Endpoint FIFO
address
Address
0xCF
0xCE
0xCD
0xCC
0xCB
Target
FDR0 Function Endpoint0
FDR1 Function Endpoint1
FDR2 Function Endpoint2
FDR3 Function Endpoint3
FDR4 Function Endpoint4
0xCA
0xC9
FDR5 Function Endpoint5
FDR6 Function Endpoint6
Bits 7...0
URDL[7:0]
Receive DMA transferred
length
Bits 7...2
Bit 1
Reserved
Activates receive DMA (DMA
for an OUT endpoint). This bit
is reset after the completion of
the DMA.
Reserved
RDMAEN
Bit 0
Bits
31...24
Bits
23...0
Reserved
RAD[23:0]
Target address in SRAM for
DMA transfers
Bits
15...9
Bits 8...0
Reserved
UTDL[8:0]
USB Transmit DMA Length
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