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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 27/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
27
Table
IntClear
Addr: 60005C hex
W
32-bits
Table
IntStatus
Addr: 600054 hex
R
32-bits
Note:
Default Value: 00000000 hex
All events related to packet RX/TX as well as events gener-
ated by compare timers can activate the
“
Bluetooth Base-
band
”
system interrupt. Conditions related to Bluetooth
Baseband FIFOs can activate
“
Bluetooth Baseband FIFOs
”
system interrupt.
Each event related to packet RX/TX, or generated by a
compare timer, is always latched on the corresponding bit
of IntStatus register. The bit is set when the event occurs.
The bit is reset when the corresponding bit of IntClear reg-
ister is set by the firmware to acknowledge the event.
However, an event related to packet RX/TX or generated
by a compare timer will produce an interrupt only if the cor-
responding bit of IntMask register has been set by firm-
ware.
Conditions related to Bluetooth Baseband FIFOs are
“
TX
FIFO almost full
”
and
“
RX FIFO almost empty
”
. These con-
ditions are not latched, but just reflected on the correspond-
ing bits of IntStatus register. Bluetooth Baseband FIFO
conditions have no corresponding bits in IntClear register,
because they will be automatically reset after proper FIFO
service by firmware.
Bluetooth Baseband FIFO conditions will produce an inter-
rupt only if the corresponding bit of IntMask register has
been set by firmware.
Bits
31...11
Bit 10
Reserved
GenPurpTim_
IntClear
TxAcCodeComplete_
IntClear
RxTxStart_
IntClear
TxPktComplete_
IntClear
RxCorrelTrig_
IntClear
RxHecFail_
IntClear
RxCrcFail_
IntClear
RxFecFail_
IntClear
RxPktHeaderRdy_
IntClear
RxPayHeaderRdy_
IntClear
RxPayloadRdy_
IntClear
Clears general purpose
compare timer interrupt.
Bit 9
Clears access Code Tx
completed interrupt.
Bit 8
Clears RX/TX start
compare timer interrupt.
Bit 7
Clears TX packet
completion interrupt.
Bit 6
Clears correlator trigger
interrupt.
Bit 5
Clears HEC fail
interrupt.
Bit 4
Clears CRC fail
interrupt.
Bit 3
Clears FEC fail interrupt.
Bit 2
Clears RX packet
header arrival interrupt.
Bit 1
Clears RX payload
header arrival interrupt.
Bit 0
Clears RX payload
completion interrupt.
Bits
31...13
Bit 12
Reserved
TxFifoAlmEmpty_
IntStatus
RxFifoAlmFull_
IntStatus
GenPurpTim_
IntStatus
TxAcCodeComplete_
IntStatus.
RxTxStart_
IntStatus
TxPktComplete_
IntStatus
RxCorrelTrig_
IntStatus
RxHecFail_
IntStatus
TX FIFO almost empty
interrupt status.
Bit 11
RX FIFO almost full
interrupt.
Bit 10
General purpose
compare timer interrupt .
Bit 9
RX/TX start compare
timer interrupt enable.
Bit 8
RX/TX start compare
timer interrupt.
Bit 7
TX packet completion
interrupt.
Bit 6
Correlator trigger
interrupt.
Bit 5
HEC fail interrupt.
Bit 4
RxCrcFail_
IntStatus
RxFecFail_
IntStatus
RxPktHeaderRdy_
IntStatus
RxPayHeaderRdy_
IntStatus
RxPayloadRdy_
IntStatus
CRC fail interrupt.
Bit 3
FEC fail interrupt.
Bit 2
RX packet header arrival
interrupt.
Bit 1
RX payload header
arrival interrupt.
RX payload completion
interrupt.
Bit 0
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