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参数资料
| 型号： | AT76C551 |
| 厂商： | ATMEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | Single Chip Bluetooth Controller(单芯片蓝牙技术控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封装： | LQFP-176 |
| 文件页数： | 40/51页 |
| 文件大小： | 845K |
| 代理商： | AT76C551 |
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AT76C551
40
Note:
Default: 00h
Control Direction
This bit is only used by Control Endpoints. It is used by FW
to indicate the direction of a control transfer. It is written by
the FW after it receives a RX SETUP interrupt. The H/W
uses this bit to determine the status phase of a control
transfer.
Data End
This bit is used only by Control Endpoints. Together with bit
1 (TX Packet Ready) it will signal the USB H/W to go to the
STATUS phase after the packet currently residing in the
FIFO is transmitted.
After the H/W completes the STATUS phase it will interrupt
the processor without clearing this bit. CAUTION: Since the
Data End bit signals
“
END OF TRANSACTION
”
any other
Endpoint controller bit set after the DATA END is not con-
sidered by the Ping-Pong controller. For this reason,
Tx_Packet Ready should be set before Data_End.
Force Stall
The processor sets this bit if it wants to force a STALL after
an unsupported request is received, or if the Host contin-
ues to ask for data after the data is exhausted. This bit
should be set at the end of any data phase or setup phase.
Stall Snd
The USB H/W sets this bit after a STALL has been sent.
The firmware uses this bit when responding to a USB Get-
Status Request.
TX Packet Ready
This bit is used for the following operations :
1.
2.
Control read transactions by a Control Endpoint.
IN transactions with DATA1 PID to complete the sta-
tus phase for a Control Endpoint, when this bit is
‘
0
’
,
but bit Data End (bit 4) is
‘
1
’
.
By a BULK IN or ISO IN or INT IN Endpoint.
The processor should write to the FIFO only if this bit is
cleared. The bit will be set after it has completed writing the
data. The data can be a zero length. For a Control Endpoint
the processor should write to the FIFO only while bit 6 (TX
Packet Requested) is set. The H/W clears this bit after it
receives an ACK. If the interrupt is enabled, clearing this bit
by the H/W, it causes an interrupt to the processor.
RX SETUP
This bit is used only by Control Endpoints to signal the pro-
cessor that the USB H/W has received a valid SETUP
packet, and that the data portion of the packet is stored in
the FIFO. The H/W will clear all other bits in this register
and will set RX SETUP. If the corresponding interrupt is
enabled, the processor will be interrupted when RX SETUP
is set. After the data has been completely read from the
FIFO the firmware should clear this bit.
RX OUT Packet
The USB H/W sets this bit after it has stored the data of an
OUT transaction in the FIFO. While this bit is set, the H/W
will NAK all OUT tokens. For Control Endpoints only, bit 7
of this register, Enable Control Write, has to be set for the
H/W to accept the OUT data. The USB H/W will not over-
write the data in the FIFO except for an early USB Setup
Request . Bit RX OUT Packet is used for the following
operations :
1.
Control write transactions by a Control Endpoint
2.
OUT transaction with DATA1 PID to complete the
status phase of a control Endpoint.
3.
By a BULK OUT or ISO OUT or INT OUT Endpoint
Setting this bit causes an interrupt to the processor if the
interrupt is enabled. The firmware clears this bit after the
FIFO are read.
TX Complete
This bit is used by H/W in a Control Endpoint to signal to
the processor that it has successfully completed certain
transactions. TX Complete is set at the completion of a:
1.
Control read data stage
2.
Status stage without data stage
3.
Status stage after a control write transaction
3.
Bit 1
W
RX OUT Packet
Indicates that the USB H/W
has decoded an OUT token
and that the data is in the
FIFO.
The H/W sets this bit to
indicate to a Control Endpoint
that it has received an ACK
handshake from the Host.
Bit 0
R
TX Complete
Address
D00037Ch
D000378h
D000374h
D000370h
D00036Ch
D000368h
D000364h
Register
FCSR0 Endpoint 0
FCSR1 Endpoint 1
FCSR2 Endpoint 2
FCSR3 Endpoint 3
FCSR4 Endpoint 4
FCSR5 Endpoint 5
FCSR6 Endpoint 6
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