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参数资料
| 型号： | DAC5688IRGCTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQCC64 |
| 封装： | 9 X 9 MM, GREEN, PLASTIC, VQFN-64 |
| 文件页数： | 19/56页 |
| 文件大小： | 1321K |
| 代理商： | DAC5688IRGCTG4 |
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SDENB
SCLK
InstructionCycle
Data TransferCycle(s)
SDIO
r/w N1
N0 A4
A3 A2
A1
A 0 D7 D6
D5 D4
D3 D2 D1
D0
SDENB
SCLK
SDIO
t s(SDENB)
t s(SDIO)
t
h ( SDIO)
t SCLK
t
SCLKH
t
SCLKL
SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010
www.ti.com
Table 2. Instruction Byte of the Serial Interface
Bit
7
6
5
4
3
2
1
0
Description
R/W
N1
N0
A4
A3
A2
A1
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC5688 and
a low indicates a write operation to DAC5688.
[N1 : N0]
Identifies the number of data bytes to be transferred per Table 3. Data is transferred MSB first.
Table 3. Number of Transferred Bytes Within One
Communication Frame
N1
N0
Description
0
Transfer 1 Byte
0
1
Transfer 2 Bytes
1
0
Transfer 3 Bytes
1
Transfer 4 Bytes
[A4 : A0]
Identifies the address of the register to be accessed during the read or write operation. For multi-byte transfers, this address
is the starting address. Note that the address is written to the DAC5688 MSB first and counts down for each byte
Figure 20 shows the serial interface timing diagram for a DAC5688 write operation. SCLK is the serial interface
clock input to DAC5688. Serial data enable SDENB is an active low input to DAC5688. SDIO is serial data in.
Input data to DAC5688 is clocked on the rising edges of SCLK.
Figure 20. Serial Interface Write Timing Diagram
Figure 21 shows the serial interface timing diagram for a DAC5688 read operation. SCLK is the serial interface
clock input to DAC5688. Serial data enable SDENB is an active low input to DAC5688. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC5688 during the data transfer
cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from DAC5688 during
the data transfer cycle(s). The SDIO/SDO data is output on the falling edge of SCLK. At the end of the data
transfer, SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when it will 3-state.
26
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5688
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