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参数资料
| 型号： | DAC5688IRGCTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQCC64 |
| 封装： | 9 X 9 MM, GREEN, PLASTIC, VQFN-64 |
| 文件页数： | 27/56页 |
| 文件大小： | 1321K |
| 代理商： | DAC5688IRGCTG4 |
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CLK 2
CLK 1
D < t_align
DA [0 : 15 ]
DB [0 : 15 ]
t s
th
(only in dual synchronous clock mode)
www.ti.com
SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010
CLOCK MODES
The DAC5688 supports several different clocking modes for generating the internal clocks for the logic and DAC.
The clocking modes are selected by programming the register bits below and summarized in Table 5.
Register
Control Bits
CONFIG1
synchr_clkin
CONFIG2
clk1_in_ena, clk1c_in_ena, diffclk_ena
CONFIG26
PLL_ena
Table 5. Summary of Clock Modes and Options
CLKO_
Programming Bits
CLK1
synchr_clkin
clk1_in_en
clk1c_in_ena
diffclk_ena
PLL_ena
Clocking Mode
Option
I/O
Dual Synchronous Clock Mode
Diff. CLK1
Input
1
0
S/E CLK1
Input
1
X
0
Dual Clock Mode
Diff. CLK1
Input
0
1
0
S/E CLK1
Input
0
1
X
0
External Clock Mode
CLKO
Output
0
X
0
PLL Clock Mode
Diff. CLK1
Input
0
1
S/E CLK1
Input
0
1
X
0
1
CLKO
Output
0
X
0
1
DUAL SYNCHRONOUS CLOCK MODE
In DUAL SYNCHRONOUS CLOCK MODE, the user provides the CLK2/C clock signal at the DAC sample rate
and also provides a divided down CLK1 at the input data rate. The CLK1 signal can be differential or
single-ended. Refer to Figure 16 for the timing diagram. In this mode the relationship between CLK2 and CLK1
(t_align) is critical and used as a synchronizing mechanism for the internal logic. This facilitates multi-DAC
synchronization by using dual external clock inputs CLK1 and CLK2 while FIFO data is always written and read
from location zero. It is highly recommended that a clock synchronizer device such as the CDCM7005 provide
both CLK2/C and CLK1/C inputs. Although CLK1 could be single-ended it is recommended to use a differential
clock to ensure proper skews between the two clock inputs.
DUAL CLOCK MODE
In DUAL CLOCK MODE, the user provides the CLK2/C clock signal at the DAC sample rate and also provides a
divided down CLK1 at the input data rate. The CLK1 signal can be differential or single-ended. Refer to Figure 32
for the timing diagram. Unlike the DUAL SYNCHRONOUS CLOCK MODE, the t_align parameter is not critical
because these clocks are not used as a synchronizing mechanism for the internal logic and the FIFO is used as
an elastic buffer for the data. Synchronizing in this mode is provided by separate control inputs.
Figure 32. DUAL (SYNCHRONOUS) CLOCK MODE Timing Diagram
Copyright 2007–2010, Texas Instruments Incorporated
33
Product Folder Link(s): DAC5688
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