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参数资料
| 型号： | DAC5688IRGCTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQCC64 |
| 封装： | 9 X 9 MM, GREEN, PLASTIC, VQFN-64 |
| 文件页数： | 9/56页 |
| 文件大小： | 1321K |
| 代理商： | DAC5688IRGCTG4 |
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SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010
Register name: CONFIG2 Address: 0x02, Default 0xE1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
diffclk_ena
clk1_in_ena
clk1c_ in_ena
clko_SE_hold
fir4_ ena
qmc_ offset_ena
qmc_ corr_ena
mixer_ena
1
0
1
diffclk_ena
:
When set (default), CLK1 and CLK1C pins are used as a differential clock input. Otherwise, CLK1 pin is used as
a single ended input.
clk1_in_ena
:
When set (default), the CLKO_CLK1 pin is configured as the CLK1 input. If cleared, the pin is configured to
output an internally generated CLKO as a clock signal for the input data.
clk1c_in_ena
:
When set (default), the LOCK_CLK1C pin is configured as the CLK1C input. If cleared, the pin is configured to
output the PLL_LOCK status.
clko_SE_hold
:
When set, the single ended (SE) clock is held to a value of ‘1’ so that the signal doesn’t toggle when using the
differential clock input.
fir4_ena
:
When set, the FIR4 Inverse SINC filter is enabled. Otherwise it is bypassed
qmc_offset_ena
:
When set, the digital Quadrature Modulator Correction (QMC) offset correction circuitry is enabled.
qmc_corr_ena
:
When set, the QMC phase and gain correction circuitry is enabled.
mixer_ena
:
When set, the Full Mixer (FMIX) is enabled. Otherwise it is bypassed.
Register name: CONFIG3 Address: 0x03, Default 0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
diffclk_dly(1:0)
clko_dly(1:0)
Reserved(3:0)
0
diffclk_dly(1:0)
:
To allow for a wider range of interfacing, the differential input clock (CLK1/CLK1C) has programmable delay
added to its tree.
diffclk_dly
Approximate additional delay
00
0
01
1.0 ns
10
2.0 ns
11
3.0 ns
clko_dly(1:0)
:
Same as above except these bits effect the single ended or internally generated clock
Register name: CONFIG4 Address: 0x04, Default 0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ser_dac_ data_ena
output_delay(1:0)
B_equals_A
A_equals_B
unused
reva
revb
0
ser_dac_data_ena
:
Muxes the ser_dac_data(15:0) to both DACs when asserted.
output_delay(1:0)
:
Delays the output to both DACs from 0 to 3 DAC clock cycles
B_equals_A
:
When set, the DACA data is driving the DACB output.
A_equals_B
:
When set, the DACB data is driving the DACA output.
Bit 4
Bit 3
DACB
DACA
Description
B_equals_A
A_equals_B
Output
0
B data
A data
Normal Output
0
1
B data
Both DACs driven by B data
1
0
A data
Both DACs driven by A data
1
A data
B data
Swapped Output
reva
:
Reverse the input bits of the A input port. MSB becomes LSB.
revb
:
Reverse the input bits of the B input port. MSB becomes LSB
Copyright 2007–2010, Texas Instruments Incorporated
17
Product Folder Link(s): DAC5688
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