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参数资料
| 型号： | DAC5688IRGCTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQCC64 |
| 封装： | 9 X 9 MM, GREEN, PLASTIC, VQFN-64 |
| 文件页数： | 8/56页 |
| 文件大小： | 1321K |
| 代理商： | DAC5688IRGCTG4 |
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SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010
www.ti.com
Register name: STATUS0 - Address: 0x00, Default 0x01
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_lock
unused
device_ID (2:0)
version(1:0)
0
1
PLL_lock
:
Asserted when the internal PLL is locked. (Read Only)
device_ID(2:0)
:
Returns ‘000’ for DAC5688. (Read Only)
version(1:0)
:
A hardwired register that contains the version of the chip. (Read Only)
Register name: CONFIG1 Address: 0x01, Default 0x0B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
insel_mode (1:0)
unused
synchr_clkin
twos
inv_inclk
interp_valule(1:0)
0
1
0
1
insel_mode(1:0)
:
Controls the expected format of the input data. For the interleaved modes, TXENABLE or the MSB of the port
that does not have data can be used to tell the chip which sample is the A sample. For TXENABLE the sample
aligned with the rising edge is A. For the MSB, it is presumed that this signal will toggle with A and B. The MSB
should be ‘1’ for A and ‘0’ for B. (*** See CONFIG23 ***)
insel_mode
Function
00
Normal input on A and B.
01
Interleaved input on A, which is de-interleaved and placed on
both A and B data paths. (*** See CONFIG23 ***)
10
Interleaved input on B, which is de-interleaved and placed on
both A and B data paths. (*** See CONFIG23 ***)
11
Half rate data on A and B inputs. This data is merge together
to form a single stream of data on the A data path.
synchr_clkin
:
This turns on the synchronous mode of the dual-clock in mode. In this mode, the CLK2/C and CLK1/C must be
synchronous in phase since the slower clock is used to synchronize dividers in the clock distribution circuit.
twos
:
When set (default), the input data format is expected to be 2’s complement. When cleared, the input is
expected to be offset-binary.
inv_inclk
:
This allows the input clock, the clock driving the input side of the FIFO to be inverted. This allows easier
registering of the data (more setup/hold time) in the single-clock mode of the device
interp_value(1:0)
:
These bits define the interpolation factor:
interp_value
Interpolation Factor
00
1X
01
2X
10
4X
11
8X
16
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5688
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