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| 型号： | DAC5688IRGCTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQCC64 |
| 封装： | 9 X 9 MM, GREEN, PLASTIC, VQFN-64 |
| 文件页数： | 42/56页 |
| 文件大小： | 1321K |
| 代理商： | DAC5688IRGCTG4 |
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www.ti.com
SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010
REVISION HISTORY
NOTE: Page numbers of previous versions may differ from current version.
Changes from Revision A (March 2008) to Revision B
Page
Changed Dual-Channel to first of title ................................................................................................................................... 1
Changed sin(x)/x from upper case to lower case ................................................................................................................. 1
Added sentence to DESCRIPTION section.."The DAC5688....multiplying PLL." ................................................................. 1
Changed to join last column 2 bottom rows as one .............................................................................................................. 1
Deleted "and External" from description of pin 25 ................................................................................................................ 3
Added sentence to description of pin 1 ................................................................................................................................ 3
Added sentence to description of pin 10,39,50,63 ............................................................................................................... 3
Added text to description of TXENABLE, pin 6 .................................................................................................................... 3
Deleted part of condition - Measured differential....to AVDD ................................................................................................ 5
Changed min value from 1.71 to 1.7, max value from 2.15 to 1.9 ....................................................................................... 5
Deleted min value -0.2 and max value 0.2, and added typ value of +/-0.2 .......................................................................... 5
Deleted "PLL = off" from 7 rows of Digital Latency description ............................................................................................ 6
Changed test conditions "NCO off" to "NCO on"; last row of Digital Latency, 2 places ....................................................... 6
Changed test conditions "NCO off" to "NCO" on next to last row of Digital Latency; and "QMC off" to "QMC on" ............. 6
Deleted min value -40 and max value 40 and added +/-20 to typ value in IIH row ............................................................. 7
Deleted min value -40 and max value 40 and added +/-20 to typ value in IIL row .............................................................. 7
Deleted 0.22xIOVDD from max value and added 0.5 in row of VOL ................................................................................... 7
Added 2 notes to EC digital specifications table .................................................................................................................. 7
Changed sentence in Offset Error: under TEST METHODOLOGY ................................................................................... 14
Added new register map table under REGISTER DESCRIPTIONS section ...................................................................... 15
Changed text in Register STATUS0 ................................................................................................................................... 16
Changed Bit 0 of Register CONFIG2 from 0 to 1 ............................................................................................................... 17
Changed text of Register CONFIG3 description ................................................................................................................ 17
Changed text of Register CONFIG4 description ................................................................................................................ 17
Deleted "Reserved" explanation from Register CONFIG5 description. .............................................................................. 18
Changed phaseoffset(15:0) to phaseoffset(15:8) in Register CONFIG7 description ......................................................... 18
Changed "Phaseadd(31:0)" to "phaseadd(31:24)" in Register CONFIG11 description ..................................................... 19
Deleted explanatory "Note" from Register CONFG14 description ..................................................................................... 20
Added text to Register CONFIG20 description. .................................................................................................................. 21
Added text to Register CONFIG21 description. .................................................................................................................. 21
Changed "Default 0x00" to "Default 0x15" for Register CONFIG23 Address .................................................................... 22
Changed text in Register CONFIG23 description ............................................................................................................... 22
Changed Register CONFIG28 description from "Reserved(7:0)" to "cleared" ................................................................... 23
Deleted "cleared" in description for Register CONFG28 .................................................................................................... 23
Deleted explanatory NOTE from Register CONFIG30 description. .................................................................................... 24
Added sentence to 1st paragraph of section "SERIAL INTERFACE" description. ............................................................. 25
Changed graphic entity for Figure 22, Magnitude Spectrum for FIR1 ................................................................................ 28
Changed text in section "Full Complex Mixer (FMIX)." ....................................................................................................... 31
Changed QOUT equation in Full Complex Mixer (FMIX) section. ........................................................................................ 31
Changed description for section "Quadrature Modulator Correction (QMC)." .................................................................... 32
Changed description for section "DAC Offset Control." ...................................................................................................... 32
Changed text in section "DUAL SYNCHRONOUS CLOCK MODE." ................................................................................. 33
Added text in section "DUAL CLOCK MODE." ................................................................................................................... 33
Copyright 2007–2010, Texas Instruments Incorporated
47
Product Folder Link(s): DAC5688
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