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参数资料
型号： DAC5688IRGCTG4
厂商： TEXAS INSTRUMENTS INC
元件分类： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQCC64
封装： 9 X 9 MM, GREEN, PLASTIC, VQFN-64
文件页数： 45/56页
文件大小： 1321K
代理商： DAC5688IRGCTG4
DAC5688
www.ti.com
SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS)
over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, DVDD, CLKVDD = 1.8 V, IOUTFS = 20 mA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
16
Bits
DC ACCURACY
INL
Integral nonlinearity
±4
LSB
1 LSB = IOUTFS/2
16
DNL
Differential nonlinearity
±2
LSB
ANALOG OUTPUT
Coarse gain linearity
± 0.04
LSB
Offset error mid code offset
0.01
%FSR
Gain error
With external reference
1
%FSR
With internal reference
0.7
%FSR
Gain mismatch
With internal reference, dual DAC mode
–2
2
%FSR
Minimum full scale output current
Nominal full-scale current, IOUTFS = 16 × IBIAS current.
2
mA
Maximum full scale output current
20
Output compliance range(1)
IOUTFS = 20 mA
AVDD
V
– 0.5V
+ 0.5V
Output resistance
300
k
Output capacitance
5
pF
REFERENCE OUTPUT
VREF
Reference output voltage
Internal Reference Mode
1.14
1.2
1.26
V
Reference output current(2)
100
nA
REFERENCE INPUT
VEXTIO
Input voltage range
External Reference Mode
0.1
1.25
V
Input resistance
1
M
CONFIG26: isbiaslpf_a and isbiaslpf_b = 0
95
Small signal bandwidth
kHz
CONFIG26: isbiaslpf_a and isbiaslpf_b = 1
472
Input capacitance
100
pF
TEMPERATURE COEFFICIENTS
Offset drift
±1
ppm of
With external reference
±15
FSR/°C
Gain drift
With internal reference
±30
Reference voltage drift
±8
ppm/°C
POWER SUPPLY
AVDD, IOVDD
3.0
3.3
3.6
V
DVDD, CLKVDD
1.7
1.8
1.9
V
PSRR
Power supply rejection ratio
±0.2
%FSR/V
AVDD + IOVDD current, 3.3V
Mode 1: ×8 Interp, PLL on, QMC = off, ISINC = off,
150
mA
DAC A+B on, FIN = 5 MHz Tone, NCO = 145 MHz,
DVDD + CLKVDD current, 1.8V
450
mA
FOUT = 150 MHz, FDAC = 500 MHz
Power Dissipation
1300
mW
AVDD + IOVDD current, 3.3V
Mode 2: ×8 Interp, PLL off, QMC = on, ISINC = on,
140
mA
DAC A+B on, FIN = 5 MHz Tone, NCO = 91 MHz
DVDD + CLKVDD current, 1.8V
520
mA
FOUT = 96 MHz, FDAC = 614.4 MHz
Power Dissipation
1400
mW
P
AVDD + IOVDD current, 3.3V
Mode 3 (Max): ×4 Interp, PLL on, QMC = on, ISINC = on,
150
mA
DAC A+B on, FIN = 5 MHz Tone, NCO = 135 MHz,
DVDD + CLKVDD current, 1.8V
700
mA
FOUT = 140 MHz, FDAC = 800 MHz
Power Dissipation
1750
1950
mW
AVDD + IOVDD current, 3.3V
Mode 4 (Sleep): ×8 Interp, PLL off, QMC = off, ISINC = off,
12
mA
DAC A+B off, FIN = 5 MHz Tone, NCO = off,
DVDD + CLKVDD current, 1.8V
15
mA
FOUT = off, FDAC = 800 MHz,
Power Dissipation
65
100
mW
(1)
The upper limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5688 device. The lower limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(2)
Use an external buffer amplifier with high impedance input to drive any external load.
Copyright 2007–2010, Texas Instruments Incorporated
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Product Folder Link(s): DAC5688
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