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参数资料
| 型号： | DAC5688IRGCTG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQCC64 |
| 封装： | 9 X 9 MM, GREEN, PLASTIC, VQFN-64 |
| 文件页数： | 30/56页 |
| 文件大小： | 1321K |
| 代理商： | DAC5688IRGCTG4 |
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DA [15:0]
A0
B0
A1
B1
AN
BN
DB15
TXENABLE
Singleeventrisingedge
flags “A” sampleif
aflag_sel = ‘1’
TogglingMSB
flags “A” sampleif
aflag_sel = ‘0’
CLK1
CLK 1
DA[15:0]
A0
A1
A2
A3
AN
A N+1
DB[15:0]
A4
A5
A 6
A7
SLLS880C – DECEMBER 2007 – REVISED AUGUST 2010
www.ti.com
INTERLEAVED BUS MODE
In INTERLEAVED BUS MODE, the user inputs dual-channel data as an interleaved single data stream to either
DA[15:] or DB[15:0] ports. The DAC5688 de-interleaves the input data stream and routes to both A and B data
paths. For input data on DA[15:0], set CONFIG1 insel_mode[15:0] = ‘01’. For input data on DB[15:0], set
CONFIG1 insel_mode[15:0] = ‘10’. In this bus mode, a separate input flag is required to distinguish an A sample
from a B sample in the interleaved data stream. This flag can either be the single event rising edge of
TXENABLE or the continuous toggling MSB of the port inactive data port. For the TXENABLE flag option, set the
CONFIG23 aflag_sel bit and the A sample will be expected to be aligned with the rising edge of TXENABLE. For
the toggling MSB option, clear the CONFIG23 aflag_sel bit and the A sample will be expected for each ‘1’ of the
MSB with the B sample is flagged for each ‘0’ of the MSB. Refer to Figure 37.
Figure 37. INTERLEAVED BUS MODE on DA[15:0] port (Dual Clock Mode)
HALF RATE BUS MODE
In HALF RATE BUS MODE, the user inputs data on both DA[15:0] and DB[15:0] ports at half rate and input logic
merges both data streams into one DAC channel (A). This mode is selected by setting CONFIG1
insel_mode[15:0] = ‘11’. Refer to Figure 38.
Figure 38. HALF RATE BUS MODE (Dual Clock Mode)
36
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5688
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