- 您现在的位置：买卖IC网 > PDF目录381697 > DDRSDRAM (SAMSUNG SEMICONDUCTOR CO. LTD.) DDR SDRAM Specification Version 0.61 PDF资料下载
参数资料
| 型号： | DDRSDRAM |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.61 |
| 中文描述： | DDR SDRAM的规格版本0.61 |
| 文件页数： | 22/49页 |
| 文件大小： | 750K |
| 代理商： | DDRSDRAM |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页
- 22 of 63 -
REV. 0.61 August 9. '99
128Mb DDR SDRAM
3.3.3 Read Interrupted by a Read
Target
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read command continues to appear on the outputs until the CAS latency from
the interrupting Read command is satisfied. At this point the data from the interrupting Read command
appears. Read to Read interval is minimum 1 Clock.
Command
< Burst Length=4, CAS Latency=2 >
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
CAS Latency=2
D
out
A
0
D
out
A
1
D
out
B
0
D
out
B
1
D
out
B
2
D
out
B
3
2
0
1
5
3
4
8
6
7
CK
CK
3.3.4 Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data conten-
tion on the I/O bus by placing the DQ
’
s(Output drivers) in a high impedance state. To insure the DQ
’
s are tri-
stated one cycle before the beginning the write operation, Burst stop command must be applied at least 2
clock cycles for CL=2 and at least 3 clock cycles for CL=2.5 before the Write command.
Command
< Burst Length=4, CAS Latency=2 >
READ
Burst Stop
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
CAS Latency=2
Dout 0
Dout 1
Din 0
Din 1
Din 2
Din 3
2
0
1
5
3
4
8
6
7
CK
CK
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read
burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been
issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up
to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
Figure 11. Read interrupted by a read timing
Figure 12. Read interrupted by a write and burst stop timing.
相关PDF资料 |
PDF描述 |
|---|---|
| DDTA113TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA114TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA115TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA123TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
| DDTA124TCA-7-F | PNP PRE-BIASED SMALL SIGNAL SOT-23 SURFACE MOUNT TRANSISTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DDRSDRAM1111 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 1.0 |
| DDR-SJE-Q2 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-Q2R-1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-R1 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
| DDR-SJE-R2 | 制造商:DOMINANT 制造商全称:DOMINANT Semiconductors 功能描述:LED Colored Resin |
发布紧急采购，3分钟左右您将得到回复。