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参数资料
| 型号： | DDRSDRAM |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.61 |
| 中文描述： | DDR SDRAM的规格版本0.61 |
| 文件页数： | 3/49页 |
| 文件大小： | 750K |
| 代理商： | DDRSDRAM |
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REV. 0.61 August 9. '99
128Mb DDR SDRAM
Target
Revision History
-
This revision history is for 64Mb and only for reference in other density.
Version 0.5 (JUN, 1997)
- First version for external release
- Center aligned DQ on reads and writes, 3.3V Vdd/Vddq, LVTTL for command and SSTL for DQ, DQS, CK and DM.
Version 0.6 (SEP. 1997)
- Changed to Edge alignedDQ on reads
- Add detailed discription for each functionality
Version 0.7 (JAN. 1998)
- Power supply: 3.3V +10%,-5% power supply for device operation (Vdd)
2.5V Power supply for I/O interface (Vddq)
- Interface: Add SSTL_2 for CK/DM (class I), DQ/DQS(class II) for KM416H431T.
* Put two part numbers, KM416H430T and KM416H431T.
- Clock input: Change to differential clock from single ended clock.
* Use CK, CK instead of CLK.
- Package: Change to 66pin TSOP-II, instead of 54pin TSOP-II
- tDQSS: Change to 0.75 ~ 1.25 tCK form 3ns ~ 1 tCK.
Add tSDQS(DQS-in setup time)
- In page 13, "DM can be ~" is modified to "DM must be ~".
- Tighten AC specs Change CK/CK hign/low level width from 0.4(min)/0.6(max)tCK to 0.45(min)/0.55(max)tCK.
-> Better input clock duty ratio from differential clock.
Version 0.8 (FEB. 1998)
- Correct pin rotation on pin 48 and 49 from 48-Vref, 49-Vss to 48-Vss, 49-Vref.
Version 0.9 (MAR. 1998)
- Change power-up sequence
. Add EMRS for DLL enable/disable
. Change DLL reset pin from A9 to A8 on MRS.
- Change speed range
. Add 133Mhz (266Mbps/pin), remove -12 (83Mhz)
- Change output load circuit
- Change input capacitance
- Add a comment on read interrupting write timing: Read command interrupting write can not be
issued at the next clock edge of write command.
- Modify the simplified state diagram on page 24.
Version 0.91 (May, 1998)
- Changed part number from KM416H430T/KM416H431T to KM416H4030T/KM416H4031T
- Added the 66pin package dimension on page 30.
- Changed Output Load Circuit 2 in page 29
- Removed CL=1.5
- Corrected typos
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| DDRSDRAM1111 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 1.0 |
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