- 您现在的位置：买卖IC网 > PDF目录16440 > EVAL-ADE5169EBZ-2 (Analog Devices Inc)BOARD EVALUATION FOR AD5169 PDF资料下载
参数资料
| 型号： | EVAL-ADE5169EBZ-2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 143/156页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5169 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是 |
| 已用 IC / 零件： | ADE5169 |
| 主要属性： | 用于汇编语言和 C 代码的 IAR 工具 |
| 次要属性： | 隔离和非隔离输出选项 |
| 已供物品： | 板，软件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页当前第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页
Data Sheet
Table 155. SPI Interrupt Status SFR (SPISTAT, Address 0xEA)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
7
6
Mnemonic
BUSY
MMERR
Default
0
0
Description
SPI peripheral busy flag.
BUSY
Result
0
The SPI peripheral is idle.
1
The SPI peripheral is busy transferring data in slave or master mode.
SPI multimaster error flag. Write a 0 to this bit to clear it.
MMERR
Result
0
A multiple master error has not occurred.
1
If the SS_EN bit (SPIMOD1, Address 0xE8[3]) is set, enabling the slave select input and asserting
the SS pin while the SPI peripheral is transferring data as a master, this flag is raised to indicate
the error. Write a 0 to this bit to clear it.
5
SPIRxOF
0
SPI receive overflow error flag. Write a 0 to this bit to clear it.
SPIRxOF
TIMODE
Result
0
X 1
The SPI2CRx SFR (Address 0x9B) contains valid data.
1
1
Set if the SPI2CRx SFR is not read before the end of the next byte transfer. If the RxOFW
bit (SPIMOD1, Address 0xE8[2]) is set and this condition occurs, SPI2CRx is overwritten.
4
SPIRxIRQ
0
SPI receive mode interrupt flag. Write a 0 to this bit to clear it.
SPIRxIRQ
TIMODE
Result
0
X 1
The SPI2CRx SFR does not contain new data.
1
0
Set when the SPI2CRx SFR contains new data. If the SPI/I 2 C interrupt is enabled, an
interrupt is generated when this bit is set. If the SPI2CRx SFR is not read before the
end of the current byte transfer, the transfer stops and the SS pin is deasserted.
1
1
The SPI2CRx SFR contains new data.
3
2
SPIRxBF
SPITxUF
0
0
Status bit for the SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx SFR clears this flag.
Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx
(Address 0x9A). Write a 0 to this bit to clear it.
1
SPITxIRQ
0
SPI transmit mode interrupt flag. Write a 0 to this bit to clear it.
SPITxIRQ
TIMODE
Result
0
X 1
The SPI2CTx SFR is full.
1
0
The SPI2CTx SFR is empty.
1
1
Set when the SPI2CTx SFR is empty. If the SPI/I 2 C interrupt is enabled, an interrupt is
generated when this bit is set. If new data is not written to the SPI2CTx SFR before the
end of the current byte transfer, the transfer stops and the SS pin is deasserted.
0
SPITxBF
0
Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
1
X = don’t care.
SPI PINS
MISO (Master In, Slave Out Data I/O Pin)
The MISO (P0.5/MISO/ZX) pin is configured as an input line
in master mode and as an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as
byte-wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (P0.4/MOSI/SDATA) pin is configured as an output
line in master mode and as an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte-
wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. The SCLK (P0.6/SCLK/T0) pin is configured as an
output in master mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)
and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).
In slave mode, the SPIMOD2 SFR (Address 0xE9) must be con-
figured with the phase and polarity of the expected input clock.
In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is important,
therefore, that the SPICPOL and SPICPHA bits (SPIMOD2[3:2])
be configured the same for the master and slave devices.
Rev. D | Page 143 of 156
相关PDF资料 |
PDF描述 |
|---|---|
| VE-J1M-EX | CONVERTER MINIMOD DC/DC 10V 75W |
| VE-21M-EX | CONVERTER MOD DC/DC 10V 75W |
| VE-21R-EX | CONVERTER MOD DC/DC 7.5V 75W |
| AD9912A/PCBZ | BOARD EVALUATION FOR AD9912 |
| H1KXH-2636M | IDC CABLE - HPK26H/AE26M/X |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EVAL-ADE5169F62EBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR ADE5169 - Boxed Product (Development Kits) 制造商:Rochester Electronics LLC 功能描述: |
| EVAL-ADE5569F62EBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
| EVAL-ADE7169EBZ-2 | 功能描述:BOARD EVALUATION FOR ADE7169F16 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
| EVAL-ADE7169F16EB | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| EVAL-ADE7169F16EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For ADE7169 制造商:Analog Devices 功能描述:EVAL BD FOR ADE7169 - Bulk |
发布紧急采购，3分钟左右您将得到回复。