参数资料
型号: EVAL-ADE5169EBZ-2
厂商: Analog Devices Inc
文件页数: 30/156页
文件大小: 0K
描述: BOARD EVALUATION FOR AD5169
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: ADE5169
主要属性: 用于汇编语言和 C 代码的 IAR 工具
次要属性: 隔离和非隔离输出选项
已供物品: 板,软件
ADE5166/ADE5169/ADE5566/ADE5569
Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB)
Data Sheet
Bit
[7:0]
Mnemonic
SCRATCH1
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC)
Bit
[7:0]
Mnemonic
SCRATCH2
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD)
Bit
[7:0]
Mnemonic
SCRATCH3
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE)
Bit
[7:0]
Mnemonic
SCRATCH4
Default
0
Description
Value can be written/read in this register. This value is maintained in all the power saving modes.
Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE)
Note that these scratch pad registers are cleared only when the part loses V DD and V BAT .
Table 26. Power Control SFR (POWCON, Address 0xC5)
Bit
7
6
Mnemonic
Reserved
METER_OFF
Default
1
0
Description
Reserved.
Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering
functions are not needed in PSM0 mode.
5
4
3
[2:0]
Reserved
COREOFF
Reserved
CD
0
0
0
010
This bit should be kept at 0 for proper operation.
Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode.
Reserved.
Controls the core clock frequency, f CORE . f CORE = 4.096 MHz/2 CD .
CD
Result ( f CORE in MHz)
000
4.096
001
2.048
010
1.024
011
0.512
100
0.256
101
0.128
110
0.064
111
0.032
Writing to the Power Control SFR (POWCON, Address 0xC5)
Writing data to the power control SFR (POWCON, Address 0xC5) involves writing 0xA7 into the key SFR (KYREG, Address 0xC1),
which is described in Table 126, followed by a write to the POWCON SFR. For example,
MOV KYREG,#0A7h
MOV POWCON,#10h
;Write KYREG to 0xA7 to get write access to the POWCON SFR
;Shut down the core
Rev. D | Page 30 of 156
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