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| 型号： | EVAL-ADE5169EBZ-2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/156页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5169 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是 |
| 已用 IC / 零件： | ADE5169 |
| 主要属性： | 用于汇编语言和 C 代码的 IAR 工具 |
| 次要属性： | 隔离和非隔离输出选项 |
| 已供物品： | 板，软件 |
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ADE5166/ADE5169/ADE5566/ADE5569
Data Sheet
Pin No.
42
43
44
45
46
47
48
49, 50
51
52, 53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
P0.3/CF2
P0.2/CF1
SDEN/P2.3/TxD2
BCTRL/INT1/P0.0
XTAL2
XTAL1
INT0
V P , V N
EA
I PA , I N
AGND
I PB
RESET
REF IN/OUT
V BAT
V INTA
V DD
V SWOUT
V INTD
DGND
V DCIN
Description
General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, or apparent power or I rms information.
General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives
instantaneous active, reactive, or apparent power or I rms information.
Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2
(Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on
power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled.
If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed.
If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains
low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3)
or as Transmitter Data Output 2 (asynchronous).
Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects V DD or V BAT to V SWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between V DD or V BAT and V SWOUT is selected internally.
A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate
oscillator circuit. An internal 6 pF capacitor is connected to this pin.
An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz.
An internal 6 pF capacitor is connected to this pin.
External Interrupt Input 0.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
Input for Emulation. When held high, this input enables the device to fetch code from internal program
memory locations. The ADE5166/ADE5169 do not support external code memory. This pin should not be left
floating.
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
Ground Reference for Analog Circuitry.
Analog Input for Second Current Channel. This input is fully differential with a maximum differential level of
±500 mV, referred to I N for specified operation. This channel also has an internal PGA.
Reset Input, Active Low.
Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical
temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 μF capacitor in
parallel with a ceramic 100 nF capacitor.
Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to V DD when
the battery is selected as the power supply.
Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Input from the Regulator. This pin is connected internally to V SWOUT when the regulator is
selected as the power supply. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic
100 nF capacitor.
3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This
pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
Ground Reference for Digital Circuitry.
Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is V SWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Rev. D | Page 18 of 156
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| EVAL-ADE7169EBZ-2 | 功能描述:BOARD EVALUATION FOR ADE7169F16 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
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