参数资料
型号: EVAL-ADE5169EBZ-2
厂商: Analog Devices Inc
文件页数: 26/156页
文件大小: 0K
描述: BOARD EVALUATION FOR AD5169
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: ADE5169
主要属性: 用于汇编语言和 C 代码的 IAR 工具
次要属性: 隔离和非隔离输出选项
已供物品: 板,软件

ADE5166/ADE5169/ADE5566/ADE5569
SPECIAL FUNCTION REGISTER (SFR) MAPPING
Table 15. SFR Mapping
Data Sheet
Mnemonic
INTPR
SCRATCH4
SCRATCH3
SCRATCH2
SCRATCH1
BATVTH
STRBPER
IPSMF
TEMPCAL
RTCCOMP
BATPR
PERIPH
DIFFPROG
B
VDCINADC
SBAUD2
LCDSEGE2
IPSME
SBUF2
SPISTAT
SPI2CSTAT
SPIMOD2
I2CADR
SPIMOD1
I2CMOD
WAV2H
WAV2M
WAV2L
WAV1H
WAV1M
WAV1L
SCON2
ACC
BATADC
MIRQSTH
MIRQSTM
MIRQSTL
MIRQENH
MIRQENM
Address
0xFF
0xFE
0xFD
0xFC
0xFB
0xFA
0xF9
0xF8
0xF7
0xF6
0xF5
0xF4
0xF3
0xF0
0xEF
0xEE
0xED
0xEC
0xEB
0xEA
0xEA
0xE9
0xE9
0xE8
0xE8
0xE7
0xE6
0xE5
0xE4
0xE3
0xE2
0xE1
0xE0
0xDF
0xDE
0xDD
0xDC
0xDB
0xDA
Description
Interrupt pins configuration SFR
(see Table 17).
Scratch Pad 4 (see Table 25).
Scratch Pad 3 (see Table 24).
Scratch Pad 2 (see Table 23).
Scratch Pad 1 (see Table 22).
Battery detection threshold
(see Table 53).
Peripheral ADC strobe period
(see Table 50).
Power management interrupt flag
(see Table 18).
RTC temperature compensation
(see Table 133).
RTC nominal compensation
(see Table 132).
Battery switchover configuration
(see Table 19).
Peripheral configuration
(see Table 20).
Temperature and supply delta
(see Table 51).
Auxiliary math (see Table 57).
V DCIN ADC value (see Table 54).
Enhanced Serial Baud Rate Control 2
(see Table 148).
LCD Segment Enable 2 (see Table 101).
Power management interrupt enable
(see Table 21).
Serial Port 2 buffer (see Table 147).
SPI interrupt status (see Table 155).
I 2 C interrupt status (see Table 159).
SPI Configuration SFR 2 (see Table 154).
I 2 C slave address (see Table 158).
SPI Configuration SFR 1 (see Table 153).
I 2 C mode (see Table 157).
Selection 2 sample MSB (see Table 31).
Selection 2 sample middle byte
(see Table 31).
Selection 2 sample LSB (see Table 31).
Selection 1 sample MSB (see Table 31).
Selection 1 sample middle byte
(see Table 31).
Selection 1 sample LSB (see Table 31).
Serial Communications Control 2
(see Table 146).
Accumulator (see Table 57).
Battery ADC value (see Table 55).
Interrupt Status 3 (see Table 43).
Interrupt Status 2 (see Table 42).
Interrupt Status 1 (see Table 41).
Interrupt Enable 3 (see Table 46).
Interrupt Enable 2 (see Table 45).
Mnemonic
MIRQENL
ADCGO
TEMPADC
IRMSH
IRMSM
IRMSL
VRMSH
VRMSM
VRMSL
PSW
TH2
TL2
RCAP2H
RCAP2L
T2CON
EADRH
EADRL
POWCON
KYREG
WDCON
STCON
EDATA
PROTKY
FLSHKY
ECON
IP
SPH
PINMAP2
PINMAP1
PINMAP0
LCDCONY
CFG
LCDDAT
LCDPTR
IEIP2
IE
DPCON
RTCDAT
RTCPTR
TIMECON2
TIMECON
P2
EPCFG
Address
0xD9
0xD8
0xD7
0xD6
0xD5
0xD4
0xD3
0xD2
0xD1
0xD0
0xCD
0xCC
0xCB
0xCA
0xC8
0xC7
0xC6
0xC5
0xC1
0xC0
0xBF
0xBC
0xBB
0xBA
0xB9
0xB8
0xB7
0xB4
0xB3
0xB2
0xB1
0xAF
0xAE
0xAC
0xA9
0xA8
0xA7
0xA4
0xA3
0xA2
0xA1
0xA0
0x9F
Description
Interrupt Enable 1 (see Table 44).
Start ADC measurement (see Table 52).
Temperature ADC value (see Table 56).
I rms measurement MSB (see Table 31).
I rms measurement middle byte
(see Table 31).
I rms measurement LSB (see Table 31).
V rms measurement MSB (see Table 31).
V rms measurement middle byte
(see Table 31).
V rms measurement LSB (see Table 31).
Program status word (see Table 58).
Timer 2 high byte (see Table 120).
Timer 2 low byte (see Table 121).
Timer 2 reload/capture high byte
(see Table 122).
Timer 2 reload/capture low byte
(see Table 123).
Timer/Counter 2 control (see Table 115).
Flash high byte address (see Table 110).
Flash low byte address (see Table 109).
Power control (see Table 26).
Key (see Table 126).
Watchdog timer (see Table 88).
Stack boundary (see Table 65).
Flash data (see Table 108).
Flash protection key (see Table 107).
Flash key (see Table 106).
Flash control (see Table 105).
Interrupt priority (see Table 82).
Stack pointer high (see Table 64).
Port 2 weak pull-up enable
(see Table 164).
Port 1 weak pull-up enable
(see Table 163).
Port 0 weak pull-up enable
(see Table 162).
LCD Configuration Y (see Table 94).
Configuration (see Table 66).
LCD data (see Table 100).
LCD pointer (see Table 99).
Interrupt Enable and Priority 2
(see Table 83).
Interrupt enable (see Table 81).
Data pointer control (see Table 79).
RTC pointer data (see Table 131).
RTC pointer address (see Table 130).
RTC Configuration 2 (see Table 129).
RTC configuration (see Table 128).
Port 2 (see Table 167).
Extended port configuration
(see Table 161).
Rev. D | Page 26 of 156
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