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参数资料
| 型号： | EVAL-ADE5169EBZ-2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 147/156页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5169 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是 |
| 已用 IC / 零件： | ADE5169 |
| 主要属性： | 用于汇编语言和 C 代码的 IAR 工具 |
| 次要属性： | 隔离和非隔离输出选项 |
| 已供物品： | 板，软件 |
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Data Sheet
Table 159. I 2 C Interrupt Status SFR (SPI2CSTAT, Address 0xEA)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
7
6
Mnemonic
I2CBUSY
I2CNOACK
Default
0
0
Description
This bit is set to Logic 1 when the I 2 C interface is used. When set, the Tx FIFO is emptied.
I 2 C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device
does not send an acknowledgement. The I 2 C communication is stopped after this event.
Write a 0 to this bit to clear it.
5
I2CRxIRQ
0
I 2 C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
Write a 0 to this bit to clear it.
4
I2CTxIRQ
0
I 2 C transmit interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
Write a 0 to this bit to clear it.
[3:2]
I2CFIFOSTAT
00
Status bits for 3- or 4-byte deep I 2 C FIFO. The FIFO monitored in these two bits is the one currently
used in I 2 C communication (receive or transmit) because only one FIFO is active at a time.
I2CFIFOSTAT
00
01
10
11
Result
FIFO empty
Reserved
FIFO half full
FIFO full
1
0
I2CACC_ERR
I2CTxWR_ERR
0
0
Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
Set when a write is attempted when the I 2 C transmit FIFO is full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
1
9
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
ACK BY
SLAVE
FRAME 2
ACK BY
MASTER
FRAME N + 1
NACK BY STOP BY
MASTER MASTER
SERIAL BUS ADDRESS BYTE
DATA BYTE 1 FROM MASTER
Figure 115. I 2 C Read Operation
DATA BYTE N FROM SLAVE
1
9
1
9
SCLK
SDATA
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
ACK BY
SLAVE
STOP BY
MASTER
Figure 116. I 2 C Write Operation
Figure 115 and Figure 116 depict I 2 C read and write operations,
respectively. Note that the LSB of the I2CADR SFR (Address 0xE9)
is used to select whether a read or write operation is performed
on the slave device. During the read operation, the master acknowl-
edgements are generated automatically by the I 2 C peripheral. The
master-generated no acknowledge (NACK) before the end of
a read operation is also automatically generated after the I2CRCT
bits in the I2CMOD SFR (Address 0xE8[4:0]) have been read from
the slave. If the I2CADR register is updated during a transmission,
the master generates a start condition instead of a stop at the end
Reading the SPI/I 2 C Receive Buffer SFR (SPI2CRx,
Address 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2crx or Mov R0, spi2crx .
A 3-cycle instruction, such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
of the read or write operation and then continues with the next
communication.
Rev. D | Page 147 of 156
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| EVAL-ADE5169F62EBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR ADE5169 - Boxed Product (Development Kits) 制造商:Rochester Electronics LLC 功能描述: |
| EVAL-ADE5569F62EBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver |
| EVAL-ADE7169EBZ-2 | 功能描述:BOARD EVALUATION FOR ADE7169F16 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
| EVAL-ADE7169F16EB | 制造商:AD 制造商全称:Analog Devices 功能描述:Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| EVAL-ADE7169F16EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For ADE7169 制造商:Analog Devices 功能描述:EVAL BD FOR ADE7169 - Bulk |
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