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| 型号： | EVAL-ADE5169EBZ-2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 47/156页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5169 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是 |
| 已用 IC / 零件： | ADE5169 |
| 主要属性： | 用于汇编语言和 C 代码的 IAR 工具 |
| 次要属性： | 隔离和非隔离输出选项 |
| 已供物品： | 板，软件 |
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Data Sheet
Table 44. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9)
ADE5166/ADE5169/ADE5566/ADE5569
Bit
[7:6]
5
4
3
2
1
0
Interrupt Enable Bit
Reserved
FAULTSIGN 1
VARSIGN 2
APSIGN
VANOLOAD
RNOLOAD 2
APNOLOAD
Description
Reserved.
When this bit is set to Logic 1, the FAULTSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1
2
This function is not available in the ADE5566 and ADE5569.
This function is not available in the ADE5166 and ADE5566.
Table 45. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)
Bit
7
6
5
4
3
2
1
0
Interrupt Enable Bit
CF2
CF1
VAEOF
REOF 1
AEOF
VAEHF
REHF 1
AEHF
Description
When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
1
This function is not available in the ADE5166 and ADE5566.
Table 46. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
Bit
[7:6]
5
4
3
2
1
0
Interrupt Enable Bit
Reserved
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Reserved.
When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
Each ADE5166/ADE5169/ADE5566/ADE5569 has two fully dif-
ferential voltage input channels. The maximum differential input
voltage for the V P /V N , I PA /I N , I PB /I N , and I P /I N input pairs is ±0.5 V.
Bit 2 to Bit 0 select the gain for the PGA in the current channel,
and Bit 7 to Bit 5 select the gain for the PGA in the voltage
channel. Figure 42 shows how a gain selection for the current
channel is made using the gain register.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain
7
0
6
0
5
0
GAIN[7:0]
4 3
0 0
2
0
1
0
0
0
selections are made by writing to the gain register (see Table 38
and Figure 41).
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
GAIN (K)
SELECTION
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
ADDR:
0x1B
I P , I Px
V IN
K × V IN
PGA2 GAIN SELECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
PGA1 GAIN SELECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
I IN
Figure 42. PGA in Current Channel
CFSIGN_OPT
RESERVED
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
Figure 41. Analog Gain Register
Rev. D | Page 47 of 156
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