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参数资料
| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 20/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
24
Revision 1.2
2.
In parallel, an address recognition cycle is performed for both the DA and the SA. The DA marks this packet as a
multicast packet. At the end of a good packet transfer, packet is forwarded to all of the local ports according to Sec-
tion 6.3.1. This multicast packet is also forwarded to the other GalNet devices in the system with the same proce-
dure as forwarding a unicast packet from one device to another. This procedure is outlined in Section 6.2. There is
a single, separate, multicast packet transfer from the source GT-48002A to each of the GalNet devices in the sys-
tem. Bit 21 of Data 0 of the BUFFER_REQUEST message (Section 10.2.2) will be set to indicate this is a multicast
packet.
3.
Packet information is also written to the PCI’s transmit descriptor which instructs the GT-48002A to send this multi-
cast packet to the CPU. This multicast packet is then forwarded directly to the CPU with the procedure outlined in
Section 6.4.
Again, if bit 22 is set, all multicast packets will
only be forwarded to the CPU and not to the local ports, nor other ports
of other GalNet devices. The CPU can then decide to what ports the multicast packet should be sent to. Only one
packet needs to be sent to each GalNet device and each device will automatically forward the packet only to the ports
that the CPU tagged for that specific Multicast packet. These ports are tagged in bits [29:22] of the END_OF_PACKET
message.
6.4
Forwarding a Packet to the CPU Directly
Systems which utilize a CPU (bit 10 of the Global Control Register, 0x140028, is set) will forward certain packets
directly to the management CPU’s memory. These packets include:
Unicast packets destined for the CPU (Device Number in the address table is equal to the CPU number)
Multicast packets
Unknown packets (if set by bit 6 in the Global Control Register, 0x140028)
BPDU messages
Sniffer packets when the CPU is the target sniffer
EASE packets
The GT-48002A contains two pointers to a sixteen block buffer area in the CPU’s memory space. The registers are
called the CPU Base Address (CBA) and CPU Base Address Shadow (CBAS.) These registers are physically located
at the same address in the GT-48002A (0x140034). The first write to this register updates the CBA register, the second
write updates the shadow register (CBAS). Figure 3 shows the data structure in the CPU memory.
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