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| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 68/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
68
Revision 1.2
17.2.10 Partition State
This signal indicates the port partition status: active - port entered partition state, inactive otherwise.
17.2.11 Secondary Port Status LED
Indicates the secondary status mode as per the inverted value of LEDMode input.
17.2.12 Pure Port Status LED
This signal will be inactive for any of the following events:
Port is disabled
Link Integrity Test Failed
Partition State Detected
Otherwise, this signal is active.
17.3
LED Signals Timing Type
17.3.1 Static LED Signals
These signals are stable for relatively long time periods. The LED indication directly reflects their current value. The stat-
ic signals are:
Port Status (LEDMode 0)
Forwarding of Unknown packets enabled
Port Configured as Sniffer
Full/Half Duplex
17.3.2 Dynamic Internal Signals:
These signals are typically active for short time periods. In order to be visible through the LED Indication Interfaces, the
GT-48002A includes a "monostable" function per each of these dynamic signals so they can be viewed on the LED in-
dication output for a period of about 62 ms in LEDMode 0 and 7.5 ms in LEDMode 1. The dynamic signals are:
Port Status (LEDMode 1)
Transmit data in progress (TxEn)
Receive data in progress (RxDV)
Collision active (Col)
Receive Buffer Full
17.4
Serial LED Interface Description
The LED serial interface consists of three outputs:
LEDClk: LEDClk is the primary timebase of the LED Indications Interface. It is a 50% duty cycle free running
clock at a fixed frequency selectable via the LEDMode input. If LEDMode is LOW, LEDClk will be 1 MHz. If
LEDMode is HIGH, LEDClk will be 202 KHz. LEDClk is HIGH-Z when Rst* is asserted.
LEDStb: LEDStb (active HIGH) indicates the beginning of the data frame. LEDStb is activated for a duration of
one LEDClk cycle once every 128 LEDClk cycles, starting from Rst* deactivation. This signal marks the begin-
ning of the 128 bit long LED data frame. LEDStb transitions occur 90 ns after LEDClk rising edge.
LEDData: The internal signals are multiplexed on the LEDData output for every data frame. LEDStb activation
signals the presence of data bit #1 (out of 128 bits) on the LEDData output. LEDData transitions occur 90 ns
after LEDClk rising edge. All internal signals accessible via LEDData are active HIGH internally and are
inverted on the LEDData output (i.e. when an internal signal is active, the data bit on the LEDData output will
be LOW). For example: If port 0 transmits data, the internal_event_transmit[0] signal is active HIGH and the
corresponding bit 9 in the LEDData serial stream is LOW.
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