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| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 62/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
62
Revision 1.2
Setting this bit should also generate a processor interrupt. The Interrupt Cause register may be read to determine the
state of the Ease_Registers, and may be written to clear the interrupt condition described above. It is possible for the
CPU to mask the interrupt condition as well as clear the interrupt condition. The GT-48002A implements a mask bit in
the Interrupt Mask register for each EASE status bit in the Interrupt Cause register. Masking and clearing the interrupts
are executed in a way that is consistent with the other interrupts supported by the GT-48002A.
Interrupt Cause Regi s te r, Offse t: 0x04 4
Interrupt Mask Register, Offs e t: 0x0 48
15.5
Sampled Packet Indication
Sampled packets are copied into the CPU’s receive buffers using the same mechanism as normal receive packets. The
only difference, from the CPU’s point of view, is that the GT-48002A will put an indication in the first word of the receive
buffer which identifies the packet as a sample. The sample indication bits specify which ports on the particular GT-
48002A the sample is associated with. It is possible for a single sample to be associated with more than one port at a
time. For example, a broadcast packet flooded to all ports may be sampled on several ports if each of their skip counters
had previously been decremented to zero.
Each GT-48002A device operates independently, so it is possible for the CPU to receive the same sample from different
GT-48002A devices. For example, a broadcast packet flooded to all ports in the system may be sampled by several GT-
48002As at the same time. Each sample will result in a separate copy of the packet being sent to the CPU. It is also
possible to sample a packet which would normally be received by the CPU. In this case, only a single copy of the packet
can be sent to the CPU. The CPU should be responsible for determining if a sampled packet should also be accepted
as a normal receive packet. In the case where a normally received packet is also a sample from multiple GT-48002A
devices (e.g. a broadcast packet), the GT-48002A must provide an indication which allows the CPU to avoid processing
duplicate packets. This indication is provided by the GT-48002A which actually received the packet from an external link.
An additional bit in the packet header indicates that the sample packet was originally received from an external link to
the CPU as opposed to the PCI system bus. Other GT-48002A devices which sampled the flooded packet only because
it was received from the PCI interface and is being transmitted on a port whose internal counter was decremented to
zero will not have this indication. These samples are “pure” samples and the CPU will know that it should not process
the packet as a normally received packet.
The first word in each 2K block holding the packet to CPU contains the following bits:
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
19
EaseReg0Empty
Ease_Register of port 0 is empty
0x0
20
EaseReg1Empty
Ease_Register of port 1 is empty
0x0
27
ErrorSASent
Error_Source message sent to CPU
0x0
other
various interrupt cause
bits
left unchanged. See register section for details
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
27:19
MaskBits
Mask the CPU interrupt line for the appropriate bits in the Interrupt
Cause register.
0x0
other
various interrupt mask
bits
left unchanged. See register section for details
0x0
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