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| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 65/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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Switched Fast Ethernet Controller
Revision 1.2
65
16.
DRAM Interface and Usage
The GT-48002A includes direct support for EDO DRAMs. The performance of EDO satisfies the required bandwidth for
data transfer, address recognition and Tx descriptor fetch/update. The DRAM interface is entirely glueless. All
accesses are performed as 32-bits. The DRAM interface is designed for 60ns EDO DRAMs and all timings are guaran-
teed to work with these devices. Refresh is performed automatically by the GT-48002A. Please refer to the Galileo-7
evaluation platform schematics for an example of EDO DRAM design with the GT-48002A.
The GT-48002A requires about 300Kbytes of the DRAM for the address table and other private data structures. The
remainder is used for packet buffers. Following power-up or system RESET, the GT-48002A device creates the MAC
Address Table in DRAM, and initializes all locations in the table to indicate that invalid entries exist in all locations.
Galileo recommends using DRAM with 256K x 16 configuration. When using this configuration, 2 DRAM chips are
required for 1 MByte, and 4 DRAM chips are required for 2 MBytes. If 1 MByte is selected, RAS0* should be con-
nected to 2 DRAM chips while RAS1* should be left unconnected.
If 2 MBytes is selected, RAS0* will control the first 1MB bank, while RAS1* will activate the second 1MB bank.
DData[31:0], DAddr[8:0], CAS*, and WE* should be connected to both banks.
Using 1 or 2 MBytes of DRAM is entirely up to the architect. 2MBytes increases the size of the Rx Buffer space as
shown in Table 3. This performance advantage must be weighed against the cost of additional memory.
17.
LED Support
The GT-48002A supports two types of LED interfaces: a serial interface and a parallel interface. The serial LED inter-
face is similar to the 3-pin LED interface of the GT-48001A device which requires a PAL to interpret the LED bit stream.
Galileo also provides reference designs and example PAL equations in the LED interface application note available on
our website.
The parallel interface offers the LED information directly via the device outputs. An external driver is required to drive
the LEDs. The mode of the parallel LED interface is selectable via the LEDMode pin.
17.1
Led Indications Interface Description
Table 32 shows the data accessible on the LED Indications Serial Interface for each of the GT-48002A ports.
17.2
Detailed LED Signal Description
17.2.1 Primary Port Status LED
The Primary Port Status LED indicates the port status in two operation modes, selectable via the LEDMode input.
Table 32: LED Signals Available
D a ta D escr ipt i o n
Sy mbol ic Sig n al N a me
Ty p e
Primary Port Status LED
primary_port_status
n/a
Transmit data in progress
transmit
dynamic
Receive data in progress
receive
dynamic
Collision active
collision
dynamic
Forwarding of unknown packets
enabled
unknown_enable
static
The port is configured as Sniffer
port_is_sniffer
static
Full/Half duplex
full_duplex
static
Receive Buffer Full
rx_buffer_full
dynamic
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