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参数资料
| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 7/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
12
Revision 1.2
RxClK[1:0]
I
Receive Clock. Provides the timing reference for the transfer of the RxDV,
RxD, RxEr signals (per port). Operates at either 25 MHz (100Mbps) or 2.5
MHz (10Mbps). The nominal frequency of RxClk (per port) should match the
nominal frequency of that port’s TxClk.
RxDV[1:0]
I
Receive Data Valid: Active HIGH. Indicates that valid data is present on the
RxD lines. Synchronous to RxClk. This input is ignored when it represents
loopback of the transmitted packet in 10BaseT mode half-duplex.
CrS[1:0]
I
Carrier Sense: Active HIGH. Indicates that either the transmit or receive
medium is non-idle. CrS is not synchronous to any clock.
MDC
O
Management Data Clock: 1 MHz clock. Provides the timing reference for the
transfer of the MDIO signal. This output may be connected to the PHY devices
of both ports.
MDIO
I/O
Management Data Input/Output: This bidirectional line is used to transfer
control information and status between the PHY and the GT-48002A. It con
forms with IEEE Std 802.3. This signal may be connected to the PHY devices
of both ports. When not in use, this pin must be connected to a pull-down resis-
tor.
Miscellaneous Interface Pins
EnAutoNeg*
I
Enable Auto-negotiation: Active LOW. The GT-48002A controls the auto-
negotiation process and configures both ports to the correct speed and duplex
as resolved by each port’s PHY. When HIGH, auto-negotiation is disabled and
the duplex setting of both ports is set based on the RESET configuration. See
Section 12.3.3 for more information on Auto-negotiation Control Per Port.
ConfigMode
I
Memory Request Configuration Mode: This pin is sampled on Rst* and is
useful for “Plug and Play” environments only. For more information, see Sec-
tion 11.4. When LOW, The GT-48002A requests 4 MBytes of PCI address
space. When the DRAM Base Address register is read back, it will report
0xFFC0.0000 (bits [21:0] are ‘0’). When HIGH, the GT-48002A requests 128
MBytes of PCI address space. When the DRAM Base Address register is read
back, it will report 0xF800.0000 (bits [27:0] are ‘0’).
ForceLinkPass*
I/O
Force Link Pass: Active LOW. This pin is sampled on Rst*. When connected
HIGH, the link status of the ports is read through the SMI (MDC/MDIO inter-
face) from the PHY devices (register#1, bit#2). When connected LOW, the link
status of all ports remains in the “link is up” state regardless of the PHY’s link
bit value. This pin should be connected to either a pull-up (normally) or a pull-
down resistor (to force the link pass). Following Rst* deassertion, this pin
becomes an output (unused - value is undefined).
LEDMode
I
LED Mode Select: Affects Port status LED, LEDClk frequency and LED ON
time values. For more information, see Section 17.
0 - select LEDMode 0
1 - select LEDMode 1
LEDData
O
LED Data: LED indicators (Link Status, Receive, Transmit, Collision,
Unknown, Port Sniffer, and Half/Full Duplex) of each port. The data is shifted
out in 128 bit long frames using the LEDClk and LEDStb pins.
LEDStb
O
LED Strobe: Indicates the beginning of valid data frame on the LEDData pin.
LEDClk
O
LED Clock: 1 MHz clock (at LEDMode 0), 202 KHz clock (at LEDMode 1).
This output is used to clock the LEDStb and LEDData outputs. During RESET,
LEDClk is tristated.
S y mbol
Ty p e
D esc ri pti o n
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