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参数资料
| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 22/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
26
Revision 1.2
Steps 3-4 are repeated. The packet transfer to the CPU is done as follows:
1.
The incoming packet is fed to the Rx FIFO and is transferred to an empty block in the Receive Buffer area of
DRAM.
2.
In parallel, an address recognition cycle is performed for both the DA and the SA. If the packet is resolved to be a
packet of the type listed at the beginning of this section, packet information is written to the PCI’s transmit descrip-
tor. This information includes the byte count and Receive Buffer Block Address which is pointed to by the Write
Pointer. When the PCI’s transmit descriptor’s Write Pointer is not equal to the Read Pointer, the source GT-48002A
sends the packet DIRECTLY to the appropriate block in the CPU main memory with the PACKET_TRANSFER
(Section 10.3.7) message using PCI master operations in multiple eight 32-bit bursts. The data is entered starting
at the 8th word (33rd byte) of the next free block. Words 1 to 7 are left empty for user purposes. The address of this
packet transfer is based upon the CBA.
3.
At the end of the packet transfer, the source GT-48002A sends the END_OF_PACKET message (Section 10.3.10)
to the first word of the block (Word #0). It also sends an interrupt via Int* to the CPU, increments the Read Pointer,
and clears the appropriate bit in its Empty List.
The CPU now has the packet buffered in its buffer area. This gives the CPU the ability to intervene in the packet’s rout-
ing or to modify the contents of the packet.
6.5
Forwarding a Packet from the CPU to a GalNet Device
The sequence for forwarding a packet from the CPU to a port in a GalNet device is the same for unicast and multicast
packets. The procedure is as follows:
1.
The CPU sends a BUFFER_REQUEST message (Section ) to the appropriate target GalNet device indicating that
there is a packet ready for transmission across the PCI bus.
2.
The target GalNet device receives this message and allocates a buffer in its DRAM. This target device then sends
a START_OF_PACKET message (Section 10.3.5) back to the CPU indicating it is ready to receive the packet. This
START_OF_PACKET message is sent to a CPU buffer location indicated by the Start Packet Base Address regis-
ter (0x140038). This address points to a CPU buffer area that can hold up to 32 START_OF_PACKET messages.
The CPU must poll this structure to know when a target GT-48002A is ready to receive a packet, and to what
address the packet should be sent. If the Byte Count field in the START_OF_PACKET message is 0, then the CPU
should not write the PACKET_TRANSFER message nor the END_OF_PACKET message to the device. This indi-
cates that either the buffers are full in the target GalNet device, or that the link is down on the target port.
3.
The CPU transfers the packet with the PACKET_TRANSFER message (Section 10.3.9) using PCI master opera-
tions in multiple eight 32-bit bursts. The packet is buffered in the Receive Buffer area of the target device’s DRAM.
After the entire packet has been transmitted, the CPU performs an additional write transaction by sending the
END_OF_PACKET message (Section 10.3.12) indicating completion of the packet transfer. This message con-
tains the Byte Count, the target Port Number, the Rx Block address, and the Packet Type. It also includes a bit
which commands the GT-48002A to generate CRC for this out-going packet or not. If the packet is a multicast
packet, the packet will only be forwarded to the ports tagged in bits [29:22] of the END_OF_PACKET message
(The CPU should NEVER write ‘1’ to bits 29:22 that had ‘0’ in in the same bits of the START_OF_PACKET mes-
sage.)
4.
Some packet information included in the END_OF_PACKET message is written to the appropriate transmit
descriptor in the target device. This information includes the Byte Count and the Receive Buffer address which is
pointed to by the Write Pointer.
5.
The Write Pointer of the outgoing port’s transmit descriptor is incremented. The target GalNet device transmits
whenever the Write Pointer is not equal to the Read Pointer.
6.
At the end of the packet transmit process, the target GalNet device increments the Read Pointer and clears the
appropriate bit in the Empty List.
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GT482 | 制造商:CORNELL DUBILIER ELECTRONICS 功能描述:Cap Ceramic 82pF 3000V SL 5% (12 X 6mm) Radial 9.5mm 85°C |
| GT48212-A6-PBB1C000 | 制造商:Marvell 功能描述: |
| GT48212-A6-PBB-C000 | 制造商:Marvell 功能描述:12 PORT E + 2 PORT FE SWITCH (MANAGED) - Trays |
| GT48300-A1-BBE1C083 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE1C083 |
| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
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