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参数资料
| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 44/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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GT-48002A Switched Fast Ethernet Controller
46
Revision 1.2
11.
PCI Bus Operation
The GT-48002A can act as either a master initiating a PCI bus operation, or as a target responding to a PCI bus oper-
ation. The GT-48002A is enabled to both master the PCI bus and respond to memory accesses after RESET.
The GT-48002A has two sets of internal registers that are accessible through the PCI interface. Internal control regis-
ters for the GT-48002A are memory mapped and accessible through standard PCI read/write operations. PCI control
registers are accessible through PCI configuration cycles.
11.1
PCI Configuration Header Registers
The GT-48002A’s PCI configuration registers are located in the standard PCI configuration header locations. Access to
these registers is through PCI configuration reads/writes with the IdSel signal asserted. PCI configuration registers
control PCI functions and return PCI information (device/vendor ID, etc.)
11.2
Accessing DRAM and Internal Registers through the PCI Interface
All GT-48002A internal control registers and the local DRAM are mapped into PCI memory space. The GT-48002A
looks at PCI address bits 31:22 to determine if it is the target for the current cycle. This results in a decode region of
4Mbytes per GT-48002A. Bit 21 of the address is used by the GT-48002A to subdecode on-chip between accesses to
DRAM and accesses to the internal registers. Bits 20:0 are used to select a specific register or memory location. Reg-
ister addresses given in this document refer to the value of bits 20:0 in the PCI address. The GT-48002A expects data
in little-endian format, as is required by the PCI specification.
The GT-48002A acts as a “medium speed” decode device, returning DevSel* in 2 clocks.
11.3
PCI Bandwidth/Performance Issues
The PCI bus has an ideal maximum bandwidth of just under 132Mbytes/sec (about 1 gigabit per second.) In systems
with many GalNet devices the bandwidth available on the PCI bus can become a performance limitation.
There are several factors that reduce the maximum achievable bus bandwidth:
Aggressiveness of the PCI arbiter. For example, the use of hidden arbitration can save cycles between adja-
cent accesses and improve overall bandwidth. Simpler arbiters will degrade bandwidth as cycles that could be
used for data transfer are used for arbitration.
The GalNet protocol does involve some overhead when compared to raw data transfer.
While performance in any given system is impossible to estimate due to design differences, Galileo Technology has
determined the theoretical maximum PCI bus loading for each 100Mbps port (see Table 23.) The bandwidth numbers
shown in this table take into account overhead for the GalNet protocol, as well as overhead for the PCI bus itself (arbi-
tration, clocks/transfer, etc.)
(Please note that the actual performance is based on several system factors. Please contact Galileo Technology if you
require assistance calculating maximum performance of your system.)
Table 23 makes the following worst-case assumptions:
Packets are being received and transmitted at full wire speed (148,800 pps for 64-byte packets)
1. Maximum number of ports to guarantee 0% packet loss at worst case loading conditions.
Table 23: PCI Bandwidth Estimates
Pack et Leng th
Maximu m P CI B a ndwi d th
R e qui re d p e r 100Mb p s P o r t
Maxi mum Nu mber o f 1 0 0Mbp s P o r t s
per P CI B u s 1
64
20.8 Mbytes/s
6
128
17.0 Mbytes/s
7
256
15.0 Mbytes/s
8
512
14.1 Mbytes/s
9
1024
13.6 Mbytes/s
9
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