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参数资料
| 型号： | GT-48002A |
| 厂商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Fast Ethernet Controller for 100BaseX(100BaseX交换式快速以太网控制器) |
| 中文描述： | 交换式快速以太网控制器（100BaseX交换式快速以太网控制器的100BaseX） |
| 文件页数： | 6/102页 |
| 文件大小： | 1001K |
| 代理商： | GT-48002A |
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Switched Fast Ethernet Controller
Revision 1.2
11
AD[31:0]
I/O
Address/Data: 32-bit multiplexed PCI address and data lines. During the first
clock of the transaction, AD[31:0] contains a physical byte address (32 bits).
During subsequent clock cycles, AD[31:0] contains data.
CBE[3:0]*
I/O
Bus Command/Byte Enable: During the address phase of the PCI transac-
tion, CBE[3:0]* provide the Bus Command. During the data phase, CBE[3:0]*
provide Byte Enables, which determine which bytes carry valid data.
Int*
O
Interrupt Request Line: Int* is asserted by the GT-48002A when one (or
more) of the bits in the Interrupt Cause register is set. This output features an
open-collector driver.
DRAM Interface
DData[31:0]
I/O
DRAM Data: 32-bit EDO DRAM data bus. These signals connect directly to
the data input/output pins of the DRAM devices.
DAddr[8:0]
I/O
DRAM Multiplexed Address Bus: In normal operation, DAddr[8:0] contain
the DRAM multiplexed row/column address. During RESET, these multiplexed
pins are sampled by the GT-48002A to indicate the Device Number and the
DRAM Parameters (see RESET Configuration Section 19.) Values are deter-
mined by connecting pull-up/pull-down resistors. The Device Number and the
DRAM Size are read by the CPU from the Status register.
RAS[1:0]*
O
Row Address Strobes: DRAM row address strobes. RAS[0]* is used for Bank
0. RAS[1]* is used for Bank 1.
CAS*
O
Column Address Strobe: DRAM column address strobe. The GT-48002A
always accesses 32-bit values and does not require a separate CAS* for each
byte.
WE*
O
Write Enable: DRAM write enable.
ChipSel*
O
FIFO Chip Select: ChipSel* asserted by the GT-48002A when a packet’s Des-
tination Port(s), Byte Count, Destination Address and Source Address are read
from the DRAM. This information can be stored in an external FIFO and
accessed by the management CPU for station-to-station connectivity matrix
information.
Media Independent
Interface
TxEn[1:0]
O
Transmit Enable: Active HIGH. This output indicates that the packet is being
transmitted. TxEn is synchronous to TxClk.
TxClk[1:0]
I
Transmit Clock: Provides the timing reference for the transfer of TxEn, TxD
signals. TxClk frequency is one fourth of the data rate (25 MHz for 100Mbps,
2.5 MHz for 10Mbps). TxClk nominal frequency should match the nominal fre-
quency of RxClk for the same port.
TxD0[3:0]
O
Transmit Data 0: Outputs the Port0 Transmit Data. Synchronous to TxClk[0].
TxD1[3:0]
O
Transmit Data 1: Outputs the Port1 Transmit Data. Synchronous to TxClk[1].
Col[1:0]
I
Collision Detect: Active HIGH. Indicates a collision has been detected on the
wire. This input is ignored in full-duplex mode, and in half-duplex mode when
TxEn of the same port is LOW. Col is not synchronous to any clock.
RxD0[3:0]
I
Receive Data 0: Port 0 Receive Data. Synchronous to RxClk[0].
RxD1[3:0]
I
Receive Data 1: Port 1 Receive Data. Synchronous to RxClk[1].
RxEr[1:0]
I
Receive Error. Active HIGH. Indicates that an error was detected in the
received frame. This input is ignored when RxDV for the same port is inactive.
Sy m b ol
Ty p e
De s c ri pti o n
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