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型号： HW-SPAR3A-SK-UNI-G
厂商： Xilinx Inc
文件页数： 122/143页
文件大小： 0K
描述： KIT STARTER W/SPARTAN-3A
产品培训模块： FPGAs Spartan3
产品变化通告： Adapter Replacement 23/May/2008
标准包装： 1
系列： Spartan®-3A
类型： FPGA
适用于相关产品： Spartan?3A FPGA，XC3S700A-FG484
所含物品： 板，线缆，文档，电源
相关产品： XC3S700A-5FTG256C-ND - IC FPGA SPARTAN-3A 256K 256FTBGA
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XC3S700A-5FGG484C-ND - IC SPARTAN-3A FPGA 700K 484FBGA
XC3S700A-5FGG400C-ND - IC SPARTAN-3A FPGA 700K 400FBGA
XC3S700A-5FG484C-ND - IC SPARTAN-3A FPGA 700K 484FBGA
XC3S700A-5FG400C-ND - IC SPARTAN-3A FPGA 700K 400FBGA
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XC3S700A-4FGG484I-ND - IC SPARTAN-3A FPGA 700K 484FBGA
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其它名称： 122-1514
Chapter 14: 10/100 Ethernet Physical Layer Interface
R
UCF Location Constraints
Figure 14-3 provides the UCF constraints for the 10/100 Ethernet PHY interface, including
the I/O pin assignment and the I/O standard used.
NET
NET
"E_COL"
"E_CRS"
LOC
LOC
=
=
"G12"
"H12"
|
|
IOSTANDARD
IOSTANDARD
=
=
LVCMOS33
LVCMOS33
|
;
PULLDOWN ;
NET
NET
NET
NET
NET
"E_MDC"
"E_MDIO"
"E_NRST"
"E_RX_CLK"
"E_RX_DV"
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
"D10"
"E10"
"D15"
"C12"
"H10"
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
;
;
SLEW = SLOW
SLEW = SLOW
SLEW = SLOW
| DRIVE = 4;
| DRIVE = 4;
| DRIVE = 4;
NET
NET
NET
NET
NET
NET
"E_RXD<0>"
"E_RXD<1>"
"E_RXD<2>"
"E_RXD<3>"
"E_RXD<4>"
"E_TX_CLK"
LOC
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
=
"G7"
"G8"
"G9"
"H9"
"G10"
"E11"
|
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
;
;
PULLUP
PULLUP
PULLUP
PULLUP
;
;
;
;
NET
NET
NET
NET
NET
"E_TX_EN"
"E_TXD<0>"
"E_TXD<1>"
"E_TXD<2>"
"E_TXD<3>"
LOC
LOC
LOC
LOC
LOC
=
=
=
=
=
"D8"
"F8"
"E7"
"E6"
"F7"
|
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
|
SLEW
SLEW
SLEW
SLEW
SLEW
=
=
=
=
=
FAST
FAST
FAST
FAST
FAST
|
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
=
4;
4;
4;
4;
4;
NET "E_TXD<4>" LOC = "B2"
| IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4 | PULLUP
;
Figure 14-3: UCF Location Constraints for 10/100 Ethernet PHY Inputs
Related Resources
Refer to the following links for additional information:
?
?
?
?
Standard Microsystems SMSC LAN8700 10/100 Ethernet PHY
h ttp://www.smsc.com/main/catalog/lan8700.html
Xilinx OPB Ethernet Media Access Controller (EMAC) (v1.02a)
h ttp://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ethernet.pdf
Xilinx OPB Ethernet Lite Media Access Controller (v1.01a)
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications the do not require support for interrupts, back-to-back data transfers, and
statistics counters.
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ethernetlite.pdf
EDK Documentation
h ttp://www.xilinx.com/ise/embedded/edk_docs.htm
122
www.xilinx.com
Spartan-3A FPGA Starter Kit Board User Guide
UG330 (v1.3) June 21, 2007
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相关代理商/技术参数
参数描述
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