参数资料
型号: HW-SPAR3A-SK-UNI-G
厂商: Xilinx Inc
文件页数: 135/143页
文件大小: 0K
描述: KIT STARTER W/SPARTAN-3A
产品培训模块: FPGAs Spartan3
产品变化通告: Adapter Replacement 23/May/2008
标准包装: 1
系列: Spartan®-3A
类型: FPGA
适用于相关产品: Spartan?3A FPGA,XC3S700A-FG484
所含物品: 板,线缆,文档,电源
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其它名称: 122-1514
R
Connectorless Debugging Port Landing Pads (J34)
UCF Location Constraints
Figure 15-11 provides the User Constraint File (UCF) constraints for the accessory headers,
including the I/O pin assignment and the I/O standard used.
# ==== 6-pin header J18 ====
# These four connections are
shared with the FX2 connector
NET "J18_IO<1>"
NET "J18_IO<2>"
NET "J18_IO<3>"
NET "J18_IO<4>"
LOC = "AA21"
LOC = "AB21"
LOC = "AA19"
LOC = "AB19"
| IOSTANDARD = LVTTL | SLEW =
| IOSTANDARD = LVTTL | SLEW =
| IOSTANDARD = LVTTL | SLEW =
| IOSTANDARD = LVTTL | SLEW =
SLOW
SLOW
SLOW
SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
# ==== 6-pin header J19 ====
# These four connections are shared with the FX2 connector
# These four connections go to through-hole pads, not to a
connector.
NET "J19_IO<1>"
NET "J19_IO<2>"
NET "J19_IO<3>"
NET "J19_IO<4>"
LOC = "Y18" | IOSTANDARD = LVTTL | SLEW =
LOC = "W18" | IOSTANDARD = LVTTL | SLEW =
LOC = "V17" | IOSTANDARD = LVTTL | SLEW =
LOC = "W17" | IOSTANDARD = LVTTL | SLEW =
SLOW | DRIVE
SLOW | DRIVE
SLOW | DRIVE
SLOW | DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
# ==== 6-pin header J20 ====
# These four connections are
shared with
the FX2 connector
NET "J20_IO<1>"
NET "J20_IO<2>"
NET "J20_IO<3>"
NET "J20_IO<4>"
LOC = "V14"
LOC = "V15"
LOC = "W16"
LOC = "V16"
| IOSTANDARD
| IOSTANDARD
| IOSTANDARD
| IOSTANDARD
= LVTTL | SLEW = SLOW
= LVTTL | SLEW = SLOW
= LVTTL | SLEW = SLOW
= LVTTL | SLEW = SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
Figure 15-11:
UCF Location Constraints for Six-Pin Accessory Headers
Connectorless Debugging Port Landing Pads (J34)
Landing pads for a connectorless debugging port are provided as the J34 header. There is
no physical connector on the board. Instead a connectorless probe, such as those available
from Agilent, provides an interface to a logic analyzer. This debugging port is intended
primarily for the Xilinx ChipScope? Pro analyer with the Agilent FPGA Dynamic Probe.
It can, however, be used with either the Agilent or Tektronix probes, without the
ChipScope analyzer, using FPGA Editor ’s probe command.
?
?
?
?
Xilinx ChipScope Pro Tool
Agilent B4655A FPGA Dynamic Probe for Logic Analyzer
Agilent 5404A/6A Pro Series Soft Touch Connector
Tektronix P69xx Probe Modules with D-Max Technology
Spartan-3A FPGA Starter Kit Board User Guide
UG330 (v1.3) June 21, 2007
135
相关PDF资料
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HW-SPAR3AN-SK-UNI-G KIT STARTER SPARTAN-3 AN
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