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型号： HW-SPAR3A-SK-UNI-G
厂商： Xilinx Inc
文件页数： 70/143页
文件大小： 0K
描述： KIT STARTER W/SPARTAN-3A
产品培训模块： FPGAs Spartan3
产品变化通告： Adapter Replacement 23/May/2008
标准包装： 1
系列： Spartan®-3A
类型： FPGA
适用于相关产品： Spartan?3A FPGA，XC3S700A-FG484
所含物品： 板，线缆，文档，电源
相关产品： XC3S700A-5FTG256C-ND - IC FPGA SPARTAN-3A 256K 256FTBGA
122-1722-ND - IC FPGA SPARTAN-3A 256K 256FTBGA
XC3S700A-4FTG256C-ND - IC FPGA SPARTAN-3A 256K 256FTBGA
XC3S700A-5FGG484C-ND - IC SPARTAN-3A FPGA 700K 484FBGA
XC3S700A-5FGG400C-ND - IC SPARTAN-3A FPGA 700K 400FBGA
XC3S700A-5FG484C-ND - IC SPARTAN-3A FPGA 700K 484FBGA
XC3S700A-5FG400C-ND - IC SPARTAN-3A FPGA 700K 400FBGA
XC3S700A-4FG484I-ND - IC SPARTAN-3A FPGA 700K 484FBGA
XC3S700A-4FG484C-ND - IC SPARTAN-3A FPGA 700K 484FBGA
XC3S700A-4FGG484I-ND - IC SPARTAN-3A FPGA 700K 484FBGA
更多...
其它名称： 122-1514
Chapter 8: PS/2 Mouse/Keyboard Port
R
Mouse
PS/2-compatible mice potentially support two modes. In polled mode, the host controller
interogates the mouse for activity. In streaming mode, the mouse reports any movement or
key presses. Streaming mode is the default operating mode.
To specifically enter streaming mode, the FPGA host must transmit a “Set Stream Mode”
command (0xEA) to the mouse. The mouse then generates a clock and data signal when
moved or when one or more keys are pressed; otherwise, these signals remain High,
indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit
words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits
(LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data
transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21,
and 32 are ‘1’ stop bits. The three eight-bit data fields contain movement data as shown in
Figure 8-4 . Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.
Mouse status byte
X direction byte
Y direction byte
1
0
L
R
C 1 XS YS XV YV P
1
0 X0 X1 X2 X3 X4 X5 X6 X7 P
1
0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P
1
Idle state
Start bit
Stop bit
Start bit
Stop bit
Start bit
Stop bit
Idle state
UG330_c8_04_032007
Figure 8-4: PS/2 Mouse Transaction
A PS/2-style mouse employs a relative coordinate system (see Figure 8-5 ), wherein
moving the mouse to the right generates a positive value in the X field, and moving to the
left generates a negative value. Likewise, moving the mouse up generates a positive value
in the Y field, and moving it down represents a negative value. The XS and YS bits in the
status byte define the sign of each value, where a ‘1’ indicates a negative value.
+Y values (YS=0)
-X values
(XS=1)
-Y values (YS=1)
+X values
(XS=0)
UG230_c8_05_021806
Figure 8-5:
The Mouse Uses a Relative Coordinate System to Track Movement
The magnitude of the X and Y values represents the rate of mouse movement. The larger
the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate
when the X or Y values exceed their maximum value, an overflow condition. A ‘1’
indicates when an overflow occurs. If the mouse moves continuously, the 33-bit
transmissions repeat every 50 ms or so.
70
www.xilinx.com
Spartan-3A FPGA Starter Kit Board User Guide
UG330 (v1.3) June 21, 2007
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