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型号： HW-SPAR3A-SK-UNI-G
厂商： Xilinx Inc
文件页数： 97/143页
文件大小： 0K
描述： KIT STARTER W/SPARTAN-3A
产品培训模块： FPGAs Spartan3
产品变化通告： Adapter Replacement 23/May/2008
标准包装： 1
系列： Spartan®-3A
类型： FPGA
适用于相关产品： Spartan?3A FPGA，XC3S700A-FG484
所含物品： 板，线缆，文档，电源
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其它名称： 122-1514
R
UCF Location Constraints
UCF Location Constraints
Figure 12-3 provides the UCF constraints for the SPI serial Flash PROM, including the I/O
pin assignment and the I/O standard used.
# some connections shared with
SPI Flash,
DAC, ADC,
and AMP
NET "SPI_MISO"
LOC = "AB20" |
IOSTANDARD
= LVTTL ;
NET "SPI_MOSI"
NET "SPI_SCK"
NET "SPI_SS_B"
NET "ALT_SS_B"
LOC = "AB14" |
LOC = "AA20" |
LOC = "Y4" |
LOC = "Y5" |
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
= LVTTL |
= LVTTL |
= LVTTL |
= LVTTL |
SLEW
SLEW
SLEW
SLEW
=
=
=
=
SLOW
SLOW
SLOW
SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
4 ;
12 ;
4 ;
4 ;
# write-protect and reset controls for Atmel AT45DB161D PROM
NET "DATAFLASH_WP"
NET "DATAFLASH_RST"
LOC = "C14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;
LOC = "C15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;
# write-protect control for ST M25P16 PROM
NET "ST_SPI_WP"
Figure 12-3:
LOC = "C13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4 ;
UCF Location Constraints for SPI Flash Connections
Creating and Programming Configuration Images for SPI Serial
Flash
Refer to the “ Master SPI Mode ” chapter in the Spartan-3 Generation Configuration User
Guide for information on how to create and format FPGA configuration images for SPI
serial Flash and how to program SPI Flash using the Xilinx iMPACT software.
?
UG332: Spartan-3 Generation Configuration User Guide
www.xilinx.com/bvdocs/userguides/ug332.pdf
SPI Flash PROM Programming Options
Starting with ISE? 9.1i software, Service Pack 2 and later, the iMPACT programming
software supports two different methods to program an attached SPI Flash PROM, as
summarized in Table 12-5 .
Using the Direct Programming Method , the programming cable communicates directly to
the SPI Flash PROM. The FPGA is not involved in the programming process and the FPGA
I/O pins that connect to the PROM must be in their high-impedance state (Hi-Z) during
programming. Hold the FPGA’s PROG_B input Low using jumper J16 to place the I/Os in
Hi-Z; the FPGA’s DONE pin remains Low.
Using the Indirect Programming Method , the programming cable connects to the FPGA’s
JTAG port. The iMPACT software first programs the FPGA with a special design that
performs the SPI PROM programming and uses the JTAG interface as a serial
communications port. During the process, the FPGA’s DONE output is High and the
DONE LED is lit because the FPGA is configured with the programming logic. All pins
that are not connected to the SPI Flash PROM or the JTAG interface have an internal pull-
up resistor to the VCCO voltage supply associated with the pin.
Spartan-3A FPGA Starter Kit Board User Guide
UG330 (v1.3) June 21, 2007
www.xilinx.com
97
相关PDF资料
PDF描述
HW-SPAR3AN-SK-UNI-G KIT STARTER SPARTAN-3 AN
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相关代理商/技术参数
参数描述
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HW-SPAR3-CPLD-DK 功能描述:STARTER KIT BUNDLE SPARTAN3/CPLD RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP
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HW-SPAR3E-DISP-DK-UNI-G-PROMO 功能描述:KIT DEV SPARTAN3E DISPLAY RoHS:是 类别:编程器，开发系统 >> 过时/停产零件编号 系列:Spartan®-3E 标准包装:1 系列:*
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