参数资料
型号: HW-SPAR3A-SK-UNI-G
厂商: Xilinx Inc
文件页数: 78/143页
文件大小: 0K
描述: KIT STARTER W/SPARTAN-3A
产品培训模块: FPGAs Spartan3
产品变化通告: Adapter Replacement 23/May/2008
标准包装: 1
系列: Spartan®-3A
类型: FPGA
适用于相关产品: Spartan?3A FPGA,XC3S700A-FG484
所含物品: 板,线缆,文档,电源
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其它名称: 122-1514
Chapter 10: Analog Capture Circuit
Header J22
DAC_REF_AB
(3.3V)
DAC_REF_CD reference voltage is nominally 3.3V.
R
The voltage is adjustable using the regulator’s I C interface.
DAC_REF_CD
(3.3V)
VINA
VINB
The reference is supplied by the LP3906 adjustable regulator, IC18.
2
LTC 6912-1 AMP
A
B
LTC 1407A-1 ADC
A/D
Channel 0
14
A/D
Channel 1
GND
VCC
(3.3V)
Spartan-3A FPGA
REF = 1.65V
14
(D16)
(AB14)
SPI_MOSI
DIN
0 1 2 3 0 1 2 3
DOUT
0
...
13
0
...
13
SDO
(T7)
(W6)
(AA20)
(W15)
AMP_CS
SPI_SCK
AMP_SHDN
CS/LD A GAIN B GAIN
SCK SPI Control Interface
SHDN
CHANNEL 1 CHANNEL 0
SCK SPI Control Interface
CONV
(Y6)
AD_CONV
AMP_DOUT
AD_DOUT
UG330_c10_02_032007
Figure 10-2: Detailed View of Analog Capture Circuit
Digital Outputs from Analog Inputs
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by Equation 10-1 .
( V IN – 1.65 V )
D [ 13:0 ] = GAIN × ------------------------------------ × 8192
1.25 V
Equation 10-1
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in Table 10-2 .
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in Figure 10-2 . Consequently, 1.65V is subtracted from the input voltage on
VINA or VINB.
The maximum range of the ADC is ± 1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
78
Spartan-3A FPGA Starter Kit Board User Guide
UG330 (v1.3) June 21, 2007
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