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参数资料
| 型号： | HY27SA081G1M-VPEB |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 1.8V PROM, 12000 ns, PDSO48 |
| 封装： | 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, WSOP1-48 |
| 文件页数： | 14/45页 |
| 文件大小： | 675K |
| 代理商： | HY27SA081G1M-VPEB |
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Rev 0.3 / May. 2004
21
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
P/E/R Controller and Cache Ready/Busy Bit (SR6)
Status Register bit SR6 has two different functions depending on the current operation.
During Cache Program operations SR6 acts as a Cache Program Ready/Busy bit, which indicates whether the Cache
Register is ready to accept new data. When SR6 is set to '0', the Cache Register is busy and when SR6 is set to '1', the
Cache Register is ready to accept new data.
During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the P/E/R Controller is active or
inactive. When the P/E/R Controller bit is set to '0', the P/E/R Controller is active (device is busy); when the bit is set
to '1', the P/E/R Controller is inactive (device is ready).
P/E/R Controller Bit (SR5)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R
Controller bit is set to '0', the P/E/R Controller is active (device is busy); when the bit is set to '1', the P/E/R Controller
is inactive (device is ready).
Cache Program Error Bit (SR1)
The Cache Program Error bit can be used to identify if the previous page (page N-1) has been successfully programed
or not in a Cache Program operation. SR1 is set to '1' when the Cache Program operation has failed to program the
previous page (page N-1) correctly. If SR1 is set to '0' the operation has completed successfully.
The Cache Program Error bit is only valid during Cache Program operations, during other operations it is Don't Care.
Error Bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to '1' when
a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to '0' the opera-
tion has completed successfully. The Error Bit SR0, in a Cache Program operation, indicates a failure on Page N.
SR4, SR3 and SR2 are Reserved
相关PDF资料 |
PDF描述 |
|---|---|
| HY27UA081G1M-TIB | 128M X 8 FLASH 3.3V PROM, 12000 ns, PDSO48 |
| HY27US08121B-TPIS | 64M X 8 FLASH 3.3V PROM, 18 ns, PDSO48 |
| HY27US08121B-FIB | 64M X 8 FLASH 3.3V PROM, 18 ns, PBGA63 |
| HY27US081G1MSES | 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48 |
| HY27US081G1MTCS | 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY27SA161G1M | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27SA1G1M | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27SAXXX | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory |
| HY27SF081G2A | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gbit (128Mx8bit / 64Mx16bit) NAND Flash |
| HY27SF081G2A-F(P) | 制造商:SK Hynix Inc 功能描述: |
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