参数资料
型号: HY27SA081G1M-VPEB
厂商: HYNIX SEMICONDUCTOR INC
元件分类: PROM
英文描述: 128M X 8 FLASH 1.8V PROM, 12000 ns, PDSO48
封装: 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, WSOP1-48
文件页数: 23/45页
文件大小: 675K
代理商: HY27SA081G1M-VPEB
Rev 0.3 / May. 2004
3
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
DESCRIPTION
The HYNIX HY27(U/S)A(08/16)1G1M series is a family of non-volatile Flash memories that use NAND cell technology.
The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264
Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus.
This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is
strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hard-
ware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER)
Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to
be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation
fails, the data can be programmed in another page without having to resend the data to be programmed.
Each device has a Cache Program feature which improves the program throughput for large files. It loads the data in a
Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array.
The devices are available in the following packages:
- 48-TSOP1 (12 x 20 x 1.2 mm)
- 48-WSOP1 (12 x 17 x 0.7 mm)
- 63-FBGA (8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch)
Three options are available for the NAND Flash family:
- Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from
page 0.
- Chip Enable Dont Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions
during the latency time do not stop the read operation.
- A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA
(Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your near-
est HYNIX Sales office.
Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to
'1'.
相关PDF资料
PDF描述
HY27UA081G1M-TIB 128M X 8 FLASH 3.3V PROM, 12000 ns, PDSO48
HY27US08121B-TPIS 64M X 8 FLASH 3.3V PROM, 18 ns, PDSO48
HY27US08121B-FIB 64M X 8 FLASH 3.3V PROM, 18 ns, PBGA63
HY27US081G1MSES 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48
HY27US081G1MTCS 128M X 8 FLASH 2.7V PROM, 45 ns, PDSO48
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