参数资料
型号: HY27SA081G1M-VPEB
厂商: HYNIX SEMICONDUCTOR INC
元件分类: PROM
英文描述: 128M X 8 FLASH 1.8V PROM, 12000 ns, PDSO48
封装: 12 X 17 MM, 0.70 MM HEIGHT, LEAD FREE, WSOP1-48
文件页数: 3/45页
文件大小: 675K
代理商: HY27SA081G1M-VPEB
Rev 0.3 / May. 2004
11
Preliminary
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Table 2. Bus Operation
Note : (1) Only for x16 devices.
(2) WP must be VIH when issuing a program or erase command.
Table 3: Address Insertion, x8 Devices
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
(2). Any additional address input cycles will be ignored.
Table4: Address Insertion, x16 Devices
Note: (1). A8 is Don
't Care in x16 devices.
(2). Any additional address input cycles will be ignored.
(3). A1 is the Least Significant Address for x16 devices.
(4). The 01h Command is not used in x16 devices.
BUS Operation
CE
ALE
CLE
RE
WE
WP
I/O0 - I/O7
I/O8 - I/O15(1)
Command Input
VIL
VIH
Rising
X(2)
Command
X
Address Input
VIL
VIH
VIL
VIH
Rising
X
Address
X
Data Input
VIL
VIH
Rising
X
Data Input
Data Output
VIL
Falling
VIH
X
Data Output
Write Protect
X
XXX
X
VIL
XX
Standby
VIH
XXX
X
Bus Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st Cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd Cycle
A16
A15
A14
A13
A12
A11
A10
A9
3rd Cycle
A24
A23
A22
A21
A20
A19
A18
A17
4th Cycle
VIL
A26
A25
Bus Cycle
I/O8-I/
O15
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st Cycle
X
A7
A6
A5
A4A3A2
A1A0
2nd Cycle
X
A16
A15
A14
A13
A12
A11
A10
A9
3rd Cycle
X
A24
A23
A22
A21
A20
A19
A18
A17
4th Cycle
VIL
A26
A25
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