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| 型号： | ICS1893AFLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 108/136页 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 标准包装： | 1,000 |
| 系列： | PHYceiver™ |
| 类型： | PHY 收发器 |
| 规程： | MII |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 1893AFLFT |
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Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
73
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
When this reserved bit is read by an STA, the ICS1893AF returns a logic zero. However, whenever an STA
writes to this reserved bit, it must use the default value specified in this data sheet. ICS uses some reserved
bits to invoke auxiliary functions. To ensure proper operation of the ICS1893AF, an STA must maintain the
default value of these bits. Therefore, ICS recommends that an STA always write the default value of any
reserved bits during all management register write operations.
Reserved bit 4.14 is a Command Override Write (CW) bit. Whenever bit 16.15 (the Command Register
Override bit) is logic:
Zero, the ICS1893AF isolates all STA writes to bit 4.14.
One, an STA can modify the value of bit 4.14.
8.6.3
Remote Fault (bit 4.13)
When the ICS1893AF Auto-Negotiation sublayer is enabled, the ICS1893AF transmits the Remote Fault bit
4.13 to its remote link partner during the auto-negotiation process. The Remote Fault bit is part of the Link
Code Word that the ICS1893AF exchanges with its remote link partner. The ICS1893AF sets this bit to logic
one whenever it detects a problem with the link, locally. The data in this register is sent to the remote link
partner to inform it of the potential problem. If the ICS1893AF does not detect a link fault, it clears bit 4.13
to logic zero.
Whenever the ICS1893AF:
Does not detect a link fault, the ICS1893AF clears bit 4.13 to logic zero.
Detects a problem with the link, during the auto-negotiation process, this bit is set. As a result, the data
on this bit is sent to the remote link partner to inform it of the potential problem.
8.6.4
IEEE Reserved Bits (bits 4.12:10)
The IEEE reserves these bits for future use. When an STA:
Reads a reserved bit, the ICS1893AF returns a logic zero.
Writes to a reserved bit, it must use the default value specified in this data sheet.
The ICS1893AF uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1893AF, an STA must maintain the default value of these bits. Therefore, ICS recommends that during
any STA write operation, an STA write the default value to all reserved bits, even those bits that are Read
Only.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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