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| 型号： | ICS1893AFLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 83/136页 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 标准包装： | 1,000 |
| 系列： | PHYceiver™ |
| 类型： | PHY 收发器 |
| 规程： | MII |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 1893AFLFT |
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ICS1893AF, Rev D 10/26/04
October, 2004
50
Chapter 7
Functional Blocks
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
7.5.9
10Base-T Operation: Jabber
The ICS1893AF has an ISO/IEC compliant Jabber Detection Function that, when enabled, monitors the
data stream sent to its Twisted-Pair Transmitter to ensure that it does not exceed the 10Base-T Jabber
activation time limit (that is, the maximum transmission time). For more information, see Section 10.5.18,
When the Jabber Detection Function detects that its transmission time exceeds the maximum Jabber
activation time limit and Jabber Detection is enabled, the ICS1893AF asserts its Collision Detect (COL)
signal. During this ISO/IEC specified ‘jabber de-activation time’, the ICS1893AF transmit data stream is
interrupted and prevented from reaching its Twisted-Pair Transmitter. During this time, when interrupting
the data stream and asserting its COL signal, the ICS1893AF transmits Normal Link Pulses and sets its
QuickPoll Detailed Status Register’s Jabber Detected bit (bit 17.2) to logic one. This bit is a latching high
(LH) bit. (For more information on latching high and latching low bits, see Section 8.1.4.1, “Latching High
The ICS1893AF provides an STA with the ability to disable the Jabber Detection Function using the Jabber
Inhibit bit (bit 18.5 in the 10Base-T Operations Register). Setting bit 18.5 to logic:
Zero (the default) enables the Jabber Detection Function.
One disables the Jabber Detection Function.
7.5.10
10Base-T Operation: SQE Test
The ICS1893AF has an ISO/IEC compliant Signal Quality Error (SQE) Test Function used exclusively for
10Base-T operations. When enabled, the ICS1893AF performs the SQE Test at the completion of each
transmitted packet (that is, whenever its TX_EN signal transitions from asserted to de-asserted). When the
ICS1893AF executes its SQE Test, it asserts the COL signal to its MAC Interface for a pre-determined time
duration (ISO/IEC specified). [For more information, see Section 10.5.17, “10Base-T: Heartbeat Timing
An ICS1893AF SQE Test Function is:
Enabled only when all the following conditions are true:
– The ICS1893AF is in node mode.
– The ICS1893AF is in half-duplex mode.
– The ICS1893AF has a valid link.
– The 10Base-T Operations Register’s SQE Test Inhibit bit (bit 18.2) is logic zero (the default).
– The ICS1893AF TX_EN signal has transitioned from asserted (high) to de-asserted (low).
Disabled whenever any of the following are true:
– The ICS1893AF is in Repeater mode.
– The ICS1893AF is in full-duplex mode.
– The ICS1893AF detects a link failure.
– The ICS1893AF SQE Test Inhibit bit (bit 18.2) in the 10Base-T Operations Register is logic one. [This
bit provides the Station Management entity (STA) with the ability to disable the SQE Test function.]
Note:
1.
In 10Base-T mode, a bit time has a typical duration of 100 ns.
2.
The SQE Test also has the name 10Base-T Heartbeat. For details on the SQE waveforms, see Section
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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