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型号： ICS1893AFLFT
厂商： IDT, Integrated Device Technology Inc
文件页数： 97/136页
文件大小： 0K
描述： PHYCEIVER LOW PWR 3.3V 48-SSOP
标准包装： 1,000
系列： PHYceiver™
类型： PHY 收发器
规程： MII
电源电压： 3.14 V ~ 3.47 V
安装类型： 表面贴装
封装/外壳： 48-BSSOP（0.295"，7.50mm 宽）
供应商设备封装： 48-SSOP
包装： 带卷 (TR)
其它名称： 1893AFLFT
Chapter 8
Management Register Set
ICS1893AF, Rev. D 10/26/04
October, 2004
63
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.3
Register 1: Status Register
Table 8-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893AF
and an STA. There are two types of status bits: some report the capabilities of the port, and some indicate
the state of signals used to monitor internal circuits.
The STA accesses the Status Register using the Serial Management Interface. During a reset, the
ICS1893AF initializes the Status Register bits to pre-defined, default values.
Note:
For an explanation of acronyms used in Table 8-5, see Chapter 1, “Abbreviations and Acronyms”.
As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
8.3.1
100Base-T4 (bit 1.15)
The STA reads this bit to learn if the ICS1893AF can support 100Base-T4 operations. Bit 1.15 of the
ICS1893AF is permanently set to logic zero, which informs an STA that the ICS1893AF cannot support
100Base-T4 operations.
Table 8-6.
Status Register (Register 1 [0x01])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
1.15
100Base-T4
Always 0. (Not supported.)
N/A
RO
–
0
7
1.14
100Base-TX full duplex
Mode not supported
Mode supported
CW
–
1
1.13
100Base-TX half duplex
Mode not supported
Mode supported
CW
–
1
1.12
10Base-T full duplex
Mode not supported
Mode supported
CW
–
1
1.11
10Base-T half duplex
Mode not supported
Mode supported
CW
–
1
8
1.10
IEEE reserved
Always 0
N/A
CW
–
0
1.9
IEEE reserved
Always 0
N/A
CW
–
0
1.8
IEEE reserved
Always 0
N/A
CW
–
0
1.7
IEEE reserved
Always 0
N/A
CW
–
0
1.6
MF Preamble
suppression
PHY requires MF
Preambles
PHY does not require
MF Preambles
RO
–
0
1.5
Auto-Negotiation
complete
Auto-Negotiation is in
process, if enabled
Auto-Negotiation is
completed
RO
LH
0
1.4
Remote fault
No remote fault detected
Remote fault detected
RO
LH
0
1.3
Auto-Negotiation ability
N/A
Always 1: PHY has
Auto-Negotiation ability
RO
–
1
9
1.2
Link status
Link is invalid/down
Link is valid/established
RO
LL
0
1.1
Jabber detect
No jabber condition
Jabber condition
detected
RO
LH
0
1.0
Extended capability
N/A
Always 1: PHY has
extended capabilities
RO
–
1
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ICS1893AFT 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR)
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ICS1893AGILF 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
ICS1893AGLF 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM
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