- 您现在的位置：买卖IC网 > PDF目录9984 > ICS1893AFLFT (IDT, Integrated Device Technology Inc)PHYCEIVER LOW PWR 3.3V 48-SSOP PDF资料下载
参数资料
| 型号： | ICS1893AFLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 44/136页 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 标准包装： | 1,000 |
| 系列： | PHYceiver™ |
| 类型： | PHY 收发器 |
| 规程： | MII |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 1893AFLFT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页
Chapter 3
Typical ICS1893AF Applications
ICS1893AF, Rev. D 10/26/04
October, 2004
15
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
– Hardwired for Node configuration (NOD/REP pin removed, tied internally to VSS). Node
configuration enables the 10M SQE test default setting and causes CRS to be asserted for either
transmit or receive activity in half duplex, or for just receive activity when in full duplex.
– Hardwired for Software mode (HW/SW pin removed, tied internally to VDD).
– Hardwired for MII interface only. (MII/SI pin removed, tied internally to VSS). In this configuration the
10baseT serial and 100baseTX 5 bit symbol interfaces are NOT supported. Applications requiring
these interfaces should use ICS1893Y-10.
In the software control configuration the 10/100, DPXSEL and ANSEL pins are outputs.
– DPXEL pin is not brought out.
– ANSEL pin is not brought out.
– 10/100 pin is brought out to indicate 100M operation. Some applications use this output to drive an
LED indicating 100M operation.
Pins LSTA (link status) and LOCK (rec. PLL locked) are not brought out.
– LSTA and LOCK provided redundant information already available with the P2LI pin. P2LI indicates
the Link is valid.
Input pin TXER is removed and tied low inside the package. The TXER function is still available by using
the Extended Control Register Reg 16 Bit 2. Most applications tied the TXER pin to VSS.
3.2
ISC1893AF Shared Features
The same silicon die is used in the ICS1893AF and ICS1893Y-10
– Only the package type is different.
The ICS1893AF offers the same.35
3.3V low power operation.
Parametric specifications and timing diagrams are the same as ICS1893Y-10.
Both the ICS1893Y-10 and the ICS1893AF incorporate Digital Signal Processing in their PMD Sub layer,
thereby allowing them to transmit and receive data with Unshielded Twisted Pair (UTP) Category 5
cables up to 150 meters in length. In addition, this ICS-patented technology enables the ICS1893Y-10
ICS1893AF to address the effects of Baseline Wander correction.
Both ICS1893AF and ICS1893Y-10 have improved 10Base-T Squelch operation.
The ICS1893AF uses the same twisted pair transmitter and receive circuits and therefore the same
recommended board layout techniques apply.
Both share improved transmit circuits resulting in a decrease in the magnitude of the 10Base-T harmonic
content generated during transmission (reference ISO/IEC 8802-3: 1993 Clause 8.3.1.3).
Both use digital PLL technology resulting in lower jitter and improved stability.
The MDIO Maintenance interface with the MDIO and MDC pins along with all internal registers are
preserved in the ICS1893AF. This enables software configuring for FD/HD, 10Base-T, 100Base-TX and
Auto-Negotiation to be configurable by the MDIO maintenance interface. Default setting is
Auto-Negotiation Enable. All register settings are the same as in the ICS1893AF datasheet.
The ICS1893AF preserves the dual-purpose LED/Phy Address control pins as in the ICS1893Y-10. The
captured address seeds the scrambler for lower EMI in for multiple Phy applications.
All Auto-Negotiation features are preserved in the ICS1893AF. The reset default mode is A_N enabled.
The A_N parallel detect feature is preserved for legacy interoperability.
Both support Management Frame (MF) Preamble Suppression.
Both support backward compatibility with the ICS1890 Management Registers.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT723641L20PF8 | IC FIFO SYNC 1024X36 120-TQFP |
| IDT723631L20PQF | IC FIFO SYNC 512X36 132-PQFP |
| ICS1893BFLFT | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| IDT723631L20PF | IC FIFO SYNC 512X36 120-TQFP |
| VE-26F-IW-F2 | CONVERTER MOD DC/DC 72V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
发布紧急采购，3分钟左右您将得到回复。