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| 型号： | ICS1893AFLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 94/136页 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 标准包装： | 1,000 |
| 系列： | PHYceiver™ |
| 类型： | PHY 收发器 |
| 规程： | MII |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 1893AFLFT |
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ICS1893AF, Rev D 10/26/04
October, 2004
60
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.2.2
Loopback Enable (bit 0.14)
This bit controls the Loopback mode for the ICS1893AF. Setting this bit to logic:
Zero disables the Loopback mode.
One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1893AF from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1893AF is in Loopback
mode, the data presented at the MAC/repeater transmit interface is internally looped back to the
MAC/repeater receive interface. The delay from the assertion of Transmit Data Enable (TXEN) to the
assertion of Receive Data valid (RXDV) is less than 512 bit times.
8.2.3
Data Rate Select (bit 0.13)
This bit provides a means of controlling the ICS1893AF data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1893AF is configured for:
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893AF isolates this bit 0.13 and uses the
10/100SEL input pin to establish the data rate for the ICS1893AF. In this Hardware mode:
– Bit 0.13 is undefined.
– The ICS1893AF provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit 17.15),
which always shows the setting of an active link.
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When the Auto-Negotiation sublayer is:
– Enabled, the ICS1893AF isolates bit 0.13 and relies on the results of the auto-negotiation process to
establish the data rate.
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
Zero selects 10-Mbps ICS1893AF operations.
One selects 100-Mbps ICS1893AF operations.
8.2.4
Auto-Negotiation Enable (bit 0.12)
This bit provides a means of controlling the ICS1893AF Auto-Negotiation sublayer. Its operation depends
on the HW/SW input pin.
When the ICS1893AF is configured for:
Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1893AF isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note:
In Hardware mode, bit 0.12 is undefined.
Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Zero:
The ICS1893AF disables the Auto-Negotiation sublayer.
The ICS1893AF bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data
rate and the duplex mode.
– One:
The ICS1893AF enables the Auto-Negotiation sublayer.
The ICS1893AF isolates bit 0.13 and bit 0.8.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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