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| 型号： | ICS1893AFLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 98/136页 |
| 文件大小： | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 标准包装： | 1,000 |
| 系列： | PHYceiver™ |
| 类型： | PHY 收发器 |
| 规程： | MII |
| 电源电压： | 3.14 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 1893AFLFT |
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ICS1893AF, Rev D 10/26/04
October, 2004
64
Chapter 8
Management Register Set
ICS1893AF Data Sheet - Release
Copyright 2004, Integrated Circuit Systems, Inc.
All rights reserved.
8.3.2
100Base-TX Full Duplex (bit 1.14)
The STA reads this bit to learn if the ICS1893AF can support 100Base-TX, full-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.14 to logic:
Zero if it cannot support 100Base-TX, full-duplex operations.
One if it can support 100Base-TX, full-duplex operations. (For the ICS1893AF, the default value of bit
1.14 is logic one, in that the ICS1893AF supports 100Base-TX, full-duplex operations.)
Bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit. [See the
description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “Register 16: Extended
8.3.3
100Base-TX Half Duplex (bit 1.13)
The STA reads this bit to learn if the ICS1893AF can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.13 to logic:
Zero if it cannot support 100Base-TX, half-duplex operations.
One if it can support 100Base-TX, half-duplex operations. (For the ICS1893AF, the default value of bit
1.13 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893AF supports 100Base-TX, half-duplex operations.)
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “Register 16:
8.3.4
10Base-T Full Duplex (bit 1.12)
The STA reads this bit to learn if the ICS1893AF can support 10Base-T, full-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.12 to logic:
Zero if it cannot support 10Base-T, full-duplex operations.
One if it can support 10Base-T, full-duplex operations. (For the ICS1893AF, the default value of bit 1.12
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893AF
supports 10Base-T, full-duplex operations.)
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in Section 8.11, “Register 16:
8.3.5
10Base-T Half Duplex (bit 1.11)
The STA reads this bit to learn if the ICS1893AF can support 10Base-T, half-duplex operations. The
ISO/IEC specification requires that the ICS1893AF must set bit 1.11 to logic:
Zero if it cannot support 10Base-T, half-duplex operations.
One if it can support 10Base-T, half-duplex operations. (For the ICS1893AF, the default value of bit 1.11
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893AF
supports 10Base-T, half-duplex operations.)
Bit 1.11 of the ICS1893AF Status Register is a Command Override Write bit., which allows an STA to alter
the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1893AFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:PHYceiver™ 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| ICS1893AG | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGI | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGILF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
| ICS1893AGLF | 制造商:ICS 制造商全称:ICS 功能描述:3.3 V 10Base-T/100Base-TX Integrated PHYceiver-TM |
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