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参数资料
型号： IDT72T6360L6BBGI
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 微控制器/微处理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324
封装： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件页数： 15/51页
文件大小： 508K
代理商： IDT72T6360L6BBGI
22
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 10, 2005
FUNCTIONAL DESCRIPTIONS
MASTER RESET AND DEVICE CONFIGURATION
Duringmasterresetthesequentialflow-controlconfigurationandsettingsare
determined, this includes the following:
1. Synchronous or Asynchronous read and write port operation
2. Bus-widthconfiguration
3. Defaultoffsetregistervalues
4. IDT standard or first word fall through (FWFT) timing mode
5. Depth expansion in IDT standard or FWFT mode
6. I/O voltage set to 2.5V or 3.3V levels
7. JTAG function enabled or disabled
8. Configuration of the external memory interface
Thestateoftheconfigurationinputsduringmasterresetwilldeterminewhich
oftheabovemodesareselected.Amasterresetcomprisesofpulsingthe
MRS
input pin from high to low for a period of time (tRS) with the configuration inputs
held in their respective states. Table 10 summarizes the configuration modes
availableduringmasterreset.Thesesignalsaredescribedindetailinthesignal
descriptionsection.
PROGRAMMABLE ALMOST EMPTY/ALMOST FULL FLAGS
The SFC has a set of programmable flags (
PAE/PAF) that can be used as
an early indicator for the empty and full boundary conditions. These flags have
anoffsetvalue(n,m)thatwilldeterminethealmostemptyandalmostfullboundary
conditions. Therearefourdefaultoffsetvaluesselectableduringmasterreset,
these values are shown in Table 11, Default Programmable Flag Offsets.
Offset values can also be programmed using the serial programming pins
(SCLK,SI,and
SWEN). TheSFChastwointernaloffsetregistersthatareused
to store the specific offset value, one for the
PAEandoneforthePAF.Thetotal
numberofbits(showninTable12,NumberofBitsRequiredforOffsetRegisters)
mustbecompletelyprogrammedtotheoffsetregisters. Theserialprogramming
sequence begins by writing data into the
PAE register followed by the PAF
register. See Figure 29, Serial Loading of Programmable Flag Registers for
theassociatedtimingdiagram.Thetotalnumberofbitsrequiredtoprogramthe
offset registers will vary depending on the type of configuration that is shown in
Figure 2a-2g, the bus-width selected, and whether EDC is used.
Thevaluesofn,mareusedsuchthatthe
PAEwillbecomeactive(LOW)when
thereareatleastonetonwordswritteninthedevice. Similarly
PAFwillbecome
active (LOW) when there are at least D – M words or more in the device, where
D is the density of the SFC.
TABLE 10 – DEVICE CONFIGURATION
Signal Pins Static State
Configuration
ASYR
0
Read port configured in asynchronous mode
1
Read port configured in synchronous mode
ASYW
0
Write port configured in asynchronous mode
1
Write port configured in synchronous mode
BM[3:0]
—
See Table 13 - Bus-Matching Configurations
FSEL[1:0]
00
Programmable flag register offset value = 127
01
Programmable flag register offset value = 1,023
10
Programmable flag register offset value = 4,095
11
Programmable flag register offset value = 16,383
FWFT
0
IDTStandardmode
1
FWFTmode
IDEM
0
Depth expansion in FWFT mode
1
Depth expansion in IDT Standard mode
IOSEL
0
I/O voltage set to 3.3V levels
1
I/O voltage set to 2.5V levels
JSEL
0
JTAG function is disabled
1
JTAG function is enabled
MIC[2:0]
—
See Table 8 - MIC[2:0] Configurations for description
MSPEED
0
External memory interface clocks set to 133MHz
1
External memory interface clocks set to 166MHz
MTYPE[1:0]
00
External memory configuration is: 4M x 32
01
Not used
10
External memory configuration is: 8M x 32
11
External memory configuration is: 16M x 16
Write Port Bus-Width
x48
x24
x12
EDC On
EDC Off
EDC On
EDC Off
EDC On
EDC Off
Configuration1(128Mb)
21
22
23
24
Configuration1(256Mb)
22
23
24
25
Configuration2(256Mb)
22
23
24
25
Configuration3(256Mb)
22
23
24
25
Configuration3(512Mb)
23
24
25
26
Configuration4(256Mb)
22
23
24
Configuration4(512Mb)
23
24
25
Configuration5(512Mb)
23
24
25
26
Configuration6(768Mb)
24
25
26
Configuration7(1Gb)
24
25
26
27
TABLE 12– NUMBER OF BITS REQUIRED FOR OFFSET REGISTERS
FSEL1
FSEL0
Offset n,m
0
127
0
1
1,023
1
0
4,095
1
16,383
TABLE11–DEFAULT PROGRAMMABLE
FLAGOFFSETS
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