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参数资料
| 型号： | IDT72T6360L6BBGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封装： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件页数： | 17/51页 |
| 文件大小： | 508K |
| 代理商： | IDT72T6360L6BBGI |
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24
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 10, 2005
TopreventdataoverflowintheFWFTmode,
IRwillgoHIGH,inhibitingfurther
write operations. Upon the completion of a valid read cycle,
IR will go LOW
allowing a write to occur. The
IR flag is updated by two WCLK cycles + tSKEW
after the valid RCLK cycle.
WENisignoredwhentheSFCisfullineitherFWFTorIDTStandardmode.
Ifasynchronousoperationofthewriteporthasbeenselected,then
WENmust
be held active.
READ STROBE AND READ CLOCK (RD/RCLK)
If synchronous operation of the read port has been selected via
ASYR,this
input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
It is permissible to stop the RCLK. Note that while RCLK is idle, the
EF/ORand
PAEflagswillnotbeupdated.TheWriteandReadClockscanbeindependent
or coincident.
IfasynchronousoperationhasbeenselectedthisinputisRD(ReadStrobe).
Data is asynchronously read from the SFC whenever there is a rising edge
on RD. In this mode the
RENandRCSinputsmustbetiedLOW.TheOEinput
is used to provide asynchronous control of the three-state Qn outputs.
WRITE CHIP SELECT (
WCS)
The
WCSdisablesallWritedataoperations(dataonly)ifitisheldHIGH.To
perform normal operations on the write port, the
WCS must be enabled, held
LOW.
READ ENABLE (
REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
Whenthe
RENinputisHIGH,theoutputregisterholdsthepreviousdataand
then no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirstword
written to an empty cache, must be requested using
REN provided thatRCS
is LOW. When the last word has been read from the SFC, the Empty Flag (
EF)
will go LOW, inhibiting further read operations.
RENisignoredwhentheSFC
is empty. Once a write is performed,
EFwillgoHIGHallowingareadtooccur.
The
EFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLKcycle.
Both
RCS and REN must be active, LOW for data to be read out on the rising
edge of RCLK.
IntheFWFTmode,thefirstwordwrittentoanemptySFCautomaticallygoes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write.
RENandRCSdonotneedtobeassertedLOW fortheFirst
Word to fall through to the output register. In order to access all other words, a
read must be executed using
REN and RCS. The RCLK LOW-to-HIGH
transition after the last word has been read from the SFC, Output Ready (
OR)
will go HIGH with a true read (RCLK with
REN=LOW;RCS=LOW),inhibiting
further read operations.
REN is ignored when the SFC is empty.
IfasynchronousoperationoftheReadporthasbeenselected,then
RENmust
be held active, (LOW).
OUTPUT ENABLE (
OE)
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When
OEisHIGH,theoutputdatabus(Qn)goes
into a high impedance state. During Master or a Partial Reset the
OEistheonly
input that can place the output bus Qn, into High-Impedance. During Reset the
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT (
RCS)
TheReadChipSelectinputprovidessynchronouscontroloftheReadoutput
port. When
RCSgoesLOW,thenextrisingedgeofRCLKcausestheQnoutputs
togototheLow-Impedancestate. When
RCSgoesHIGH,thenextRCLKrising
edgecausestheQnoutputstoreturntoHIGHZ.DuringaMasterorPartialReset
the
RCSinputhasnoeffectontheQnoutputbus,OEistheonlyinputthatprovides
High-ImpedancecontroloftheQnoutputs.If
OEisLOWtheQndataoutputswill
be Low-Impedance regardless of
RCSuntilthefirstrisingedgeofRCLKafter
a Reset is complete. Then if
RCS is HIGH the data outputs will go to High-
Impedance.
The
RCSinputdoesnoteffecttheoperationoftheflags. Forexample,when
the first word is written to an empty SFC, the
EFwillstillgofromLOWtoHIGH
based on a rising edge of RCLK
, regardless of the state of the RCS input.
Also,whenoperatingtheSFCinFWFTmodethefirstwordwrittentoanempty
SFC will still be clocked through to the output register based on RCLK,
regardless of the state of
RCS. For this reason the user must take care when
a data word is written to an empty SFC in FWFT mode. If
RCSisdisabledwhen
anemptySFCiswritteninto,thefirstwordwillfallthroughtotheoutputregister,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take
RCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z.
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW.
A rising edge of RCLK with
RCS and REN active LOW, will read out the next
word.CaremustbetakensoasnottolosethefirstwordwrittentoanemptySFC
when
RCS is HIGH. See Figure 15 for Read Chip Select. If asynchronous
operation of the Read port has been selected, then
RCS must be held active,
(tied LOW).
OE provides three-state control of Qn.
BUS-MATCHING (BM[3:0])
Thesepinsareusedtodefinetheinputandoutputbuswidths. DuringMaster
Reset,thestateofthesepinsisusedtoconfigurethedevicebussizes. Allflags
will operate on the word/byte size boundary as defined by the selection of bus
width.SeeFigures22-25forBus-MatchingConfigurations.SeeTable13,Bus-
Matching Configurations for the available configurations.
BM3
BM2
BM1
BM0
Read Bus
Write Bus
Width
1
0
x36
1
0
1
x18
x36
1
0
1
x9
x36
1
0
1
x36
x18
1
x36
x9
0
1
x18
0
1
0
1
x9
x18
0
1
x18
x9
0
1
x9
TABLE 13 – BUS-MATCHINGS
FLAG SELECT (FSEL[1:0])
Duringmasterreset,theseinputswillselectoneoffourdefaultvaluesforthe
programmable flags
PAE and PAF. The selected value (listed in Table 14 -
MTYPE[1:0] Configurations) will apply to both
PAEand PAF offset.
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