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参数资料
| 型号： | IDT72T6360L6BBGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA324 |
| 封装： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件页数： | 18/51页 |
| 文件大小： | 508K |
| 代理商： | IDT72T6360L6BBGI |
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25
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OCTOBER 10, 2005
MEMORY CONFIGURATION (MIC[2:0])
These signals enable the EDC feature of the device. See Table 8, MIC[2:0]
Configurations for more information.
MEMORY SPEED (MSPEED)
Thispinisusedtodeterminethememoryinterfaceclockspeed(CKand
CK)
for the external memory used. If MSPEED is HIGH, external memory CK and
CKwillbeoperatingat166MHz.IfMSPEEDisLOW,thentheexternalmemory
CK and
CK will be operating at 133MHz.
MASTER CLOCK (MCLK)
33MHz reference clock used to generate CK and
CK for external memory
interface.
MEMORY TYPE (MTYPE[1:0])
These signals select the density configuration of the external DDR SDRAM
used. See Table 14, for selection of the memory density configuration.
modes.SeeFigure29,LoadingofProgrammableFlagRegisters,forthetiming
diagram.
I/O VDDQ SELECT (IOSEL)
This input determines whether the inputs and outputs will tolerate a 2.5V or
3.3Vvoltagesignals.IfIOSELisHIGH,thenallI/Oswillbe2.5Vlevels.IfIOSEL
is LOW, then all I/Os will be 3.3V levels. See Table 15 for a list of affected I/O
signals.
DEPTH EXPANSION MODE SELECT (IDEM)
This select pin is used for depth expansion configuration in IDT Standard
mode. If this pin is tied HIGH, then the
FF/IR signal will be inverted to provide
aseamlessdepthexpansioninterface.IfthispinistiedLOW,thedepthexpansion
in IDT Standard mode will be deactivated. For details on depth expansion
configuration, see Figure 34, Depth Expansion Configuration in IDT Standard
Mode and Figure 35, Depth Expansion Configuration in FWFT Mode.
SERIAL READ ENABLE (
SREN)
The serial read enable input is an enable used for reading the value of the
programmable offset registers. By setting the JSEL pin to LOW, the serial data
output(SO)andserialclock(SCLK)signalscanbeusedwith
SRENtoprogram
the offset registers. When
SRENisLOW,dataattheSOcanbereadfromthe
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
readenableisHIGH,thereadingoftheoffsetregisterswillstop.
SRENmustbe
kept LOW in order to read the entire contents of the scan out register. If at any
point
SRENistoggledHIGH,thereadpointeroftheoffsetregisterswillresetto
the first location. The next time
SRENisenabledthefirstcontentsintheoffset
register will be read back. Serial read enable functions the same way in both
IDT Standard and FWFT modes. See Figure 30, Reading of Programmable
Flag Registers, for the timing diagram.
SERIAL WRITE ENABLE (
SWEN)
The serial write enable input is an enable used for serial programming of the
programmableoffsetregisters. BysettingtheJSELpintoLOW,theserialinput
(SI) and serial clock (SCLK) signals can be used with
SWEN to program the
offsetregisters.When
SWENisLOW,dataattheSIinputareloadedintotheoffset
register, one bit for each LOW-to-HIGH transition of SCLK. When
SWEN is
HIGH,theoffsetregistersretaintheprevioussettingsandnooffsetsareloaded.
Serial write enable functions the same way in both Standard IDT and FWFT
Density Configurations
4M x 32
8M x 32
Reserved
16M x 16
MTYPE0
00
1
MTYPE1
01
0
1
TABLE14–MTYPE[1:0]CONFIGURATIONS
TABLE 15 – PARAMETERS AFFECTED
BY I/O SELECTION
SFC I/O affected by I/O selection
DDR SDRAM I/O -
NOTaffected(1)
ASYR
MIC[2:0]
RCS
A[12:0]
DQ[63:0]
ASYW
MCLK
REN
BA[1:0]
DQS[7:0]
BM[3:0]
MRS
SREN
CK
RAS
D[35:0]
MSPEED
SWEN
CK
WE
EF/OR
MTYPE[1:0]
TCK/SCLK
CAS
FF/IR
OE
TDI/SI
FSEL[1:0]
PAE
TDO/SO
FWFT
PAF
TMS
IDEM
PRS
WCLK/WR
IOSEL
Q[35:0]
WCS
JSEL
RCLK/RD
WEN
NOTE
:
1. I/O to DDR SDRAM is not affected by I/O voltage selection
JTAG SELECT (JSEL)
This input determines whether the JTAG port will be activated or deactivated.
If JSEL is HIGH, then the JTAG port is activated and the associated JTAG pins
(TCK, TDI, TDO, TMS) are used for the boundary-scan function. If JSEL is
LOW, the JTAG port is disabled and the serial programming pins (SCLK, SI,
SO) will be used to program and read the offset register values for
PAE and
PAF. See Figure 29 and 30, Serial Loading and Reading of Programmable
Registers for information on how to program the registers.
OUTPUTS
FULL FLAG/INPUT READY (
FF/IR)
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (
FF) function
is selected. When the SFC is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the SFC is not full. If no reads are performed
afterareset(either
MRSorPRS),FFwillgoLOWSeeFigure12,FullBoundary
- IDT Standard Mode, for the relevant timing information.
InFWFTmode,theInputReady(
IR)functionisselected.IRgoesLOWwhen
memory space is available for writing in data. When there is no longer any free
space left,
IR goes HIGH, inhibiting further write operations. If no reads are
performedafterareset(either
MRSorPRS),IRwillgoHIGHseeFigure9Write
First Word Cycles - FWFT Mode, for the relevant timing information.
The
IR statusnotonlymeasuresthecontentsoftheSFCmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to de-assert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
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