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参数资料
型号： M38D59GC-XXXFP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封装： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件页数： 64/142页
文件大小： 2004K
代理商： M38D59GC-XXXFP
Rev.3.04
May 20, 2008
Page 28 of 134
REJ03B0158-0304
38D5 Group
INTERRUPTS
The 38D5 Group interrupts are vector interrupts with a fixed
priority scheme, and generated by 16 sources among 17 sources:
6 external, 10 internal, and 1 software.
The interrupt sources, vector addresses(1), and interrupt priority
are shown in Table 11.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 18 shows an interrupt control diagram.
An interrupt requests is accepted when all of the following
conditions are satisfied:
Interrupt disable flag ................................ “0”
Interrupt request bit .................................. “1”
Interrupt enable bit ................................... “1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
NOTES:
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
3. INT0, and INT1 input pins are selected by the interrupt edge selection register (INTEDGE).
Table 11
Interrupt vector addresses and priority
Interrupt Source
Priority
Vector Addresses(1)
Interrupt Request
Generating Conditions
Remarks
High
Low
Reset(2)
1FFFD16
FFFC16
At reset
Non-maskable
INT0 (INT00 or
INT01)(3)
2FFFB16
FFFA16
At detection of either rising or falling
edge of INT0 input
External interrupt (active edge selectable)
INT1 (INT10 or
INT11)(3)
3FFF916
FFF816
At detection of either rising or falling
edge of INT1 input
External interrupt (active edge selectable)
INT2
4FFF716
FFF616
At detection of either rising or falling
edge of INT2 input
Valid when INT2 interrupt is selected
External interrupt (active edge selectable)
Key input
(key-on wakeup)
5FFF516
FFF416
At falling of ports P20
P23, P44P47
input logical level AND
Valid when Key input interrupt is
selected External interrupt (falling valid)
Timer X
6
FFF316
FFF216
At timer X underflow
Timer 1
7
FFF116
FFF016
At timer 1 underflow
Timer 2
8
FFEF16
FFEE16
At timer 2 underflow
Timer 3
9
FFED16
FFEC16
At timer 3 underflow
Timer 4
10
FFEB16
FFEA16
At timer 4 underflow
Serial I/O1 receive
11
FFE916
FFE816
At completion of serial I/O1 data receive Valid only when serial I/O1 is selected
Serial I/O1 transmit
12
FFE716
FFE616
At completion of serial I/O1 transmit
shift or transmit buffer is empty
Valid only when serial I/O1 is selected
Serial I/O2
13
FFE516
FFE416
At completion of serial I/O2 data
transmit/receive
CNTR0
14
FFE316
FFE216
At detection of either rising or falling
edge of CNTR0 input
External interrupt (active edge selectable)
Timer Y
15
FFE116
FFE016
At timer Y underflow
CNTR1
At detection of either rising or falling
edge of CNTR1 input
External interrupt (active edge selectable)
A/D conversion
16
FFDF16
FFDE16
At completion of A/D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
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