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| 型号： | M38D59GC-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件页数： | 98/142页 |
| 文件大小： | 2004K |
| 代理商： | M38D59GC-XXXFP |
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Rev.3.04
May 20, 2008
REJ03B0158-0304
38D5 Group
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example,
because of a software run-away). The watchdog timer consists of
an 8-bit counter.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register, each
watchdog timer is set to “FF16”. Instructions such as STA, LDM
and CLB to generate the write signals can be used.
The written data in bits 7, 6 or 5 are not valid, and the above
values are set.
Bits 7 to 5 can be rewritten only once after releasing reset.
After rewriting it is disable to write any data to this bit. This bit
becomes “0” after reset.
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the
watchdog timer control register. An internal reset occurs at an
underflow of the watchdog timer. Then, reset is released after the
reset release time is elapsed, the program starts from the reset
vector address.
Normally, writing to the watchdog timer control register before
an underflow of the watchdog timer is programmed. If writing to
the watchdog timer control register is not executed, the watchdog
timer does not operate.
When reading the watchdog timer control register is executed,
the contents of the high-order 5-bit counter, the count source
selection bit 2 (bit 5), the STP instruction function selection bit
(bit 6), and the count source selection bit (bit 7) are read out.
Bit 6 of Watchdog Timer Control Register
1. When bit 6 of the watchdog timer control register is “0”, the
MCU enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer
restarts counting (Note 1). When executing the WIT
instruction, the watchdog timer does not stop.
2. When bit 6 is “1”, execution of STP instruction causes an
internal reset. When this bit is set to “1” once, it cannot be
rewritten to “0” by program. Bit 6 is “0” at reset.
3. The time until the underflow of the watchdog timer register
after writing to the watchdog timer control register is exe-
cuted is as follows (when the bit 7 of the watchdog timer
control register is “0”);
4. at XIN mode (f(XIN) = 8 MHz): 32.768 ms
5. at low-speed mode (f(XCIN) = 32 KHz): 8.19s
<Notes>
1. The watchdog timer continues to count even during the wait
time set by timer 1 and timer 2 to release the stop state and
in the wait mode. Accordingly, write to the watchdog timer
control register to not underflow the watchdog timer in this
time.
2. When the on-chip oscillator is selected by the watchdog
timer count source selection bit 2, the on-chip oscillator
forcibly oscillates and it cannot be stopped. Also, in this
time, set the STP instruction function selection bit to “1” at
this time.
Select “0” (
φSOURCE) the watchdog timer count source
selection bit 2 at the system which on-chip oscillator is
stopped.
Fig. 52 Block diagram of Watchdog timer
Fig. 53 Structure of Watchdog timer control register
1/1024
Watchdog
timer H (5)
Watchdog timer
count source
selection bit
Reset
circuit
“FF16” is set when
watchdog timer
control register is
written to.
Internal reset
Wait until reset release
Watchdog
timer L (3)
1/4
“0”
“1”
φ SOURCE
“0”
“1”
On-chip oscillator 1/4
Watchdog timer count
source selection bit 2
Data bus
Note1:
φSOURCE indicates the followings:
XIN input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
(1)
STP instruction function selection bit
Undefined instruction
Reset
STP instruction
RESET
Watchdog timer H (for read-out of high-order 5 bit)
“FF16” is set to watchdog timer by writing to these bits.
Watchdog timer count source selection bit 2
0 :
φSOURCE
1 : On-chip oscillator/4
Watchdog timer control register
(WDTCON : address 002916)
b7
b0
Watchdog timer count source selection bit
0 : Count source/1024
1 : Count source/4
STP instruction function selection bit
0 : Entering stop mode by execution of STP instruction
1 : Internal reset by execution of STP instruction
Notes 1:
φSOURCE indicates the followings:
XIN input in the frequency/2, 4 , or 8 mode
On-chip oscillator divided by 4 in the on-chip
oscillator mode
Sub-clock in the low-speed mode
2: When the on-chip oscillator is selected by the
watchdog timer count source selection bit 2,
set the STP instruction function selection bit
to “1”.
Select
φ(SOURCE) as the count source at the
system which on-chip oscillator is stopped.
3: Bits 7 to 5 can be rewritten only once after reset.
After rewriting it is disable to write any data to this bit.
(1)
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